ATtiny44 datasheet(94/236 Pages) ATMEL

94 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

ister since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits,

the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 105.

12.6.1

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (1x) bit. Forcing compare match will not set the

OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare

match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or

toggled).

12.6.2

Compare Match Blocking by TCNT1 Write

All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the

same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

12.6.3

Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT1 when using any of the Output Compare

channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect wave-

form generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP

values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.

Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC1x value is to use the Force Output Com-

pare (1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing

between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value.

Changing the COM1x1:0 bits will take effect immediately.

12.7

Compare Match Output Unit

The Compare Output Mode (COM1x1:0) bits have two functions. The Waveform Generator uses

the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.

Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 12-5 on page 95 shows

a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O

bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control

registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to

the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system

reset occur, the OC1x Register is reset to “0”.

ATtiny44 Datasheet(PDF) 94 Page - ATMEL Corporation

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