ATtiny44 datasheet(124/236 Pages) ATMEL

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8006H–AVR–10/09

ATtiny24/44/84

14.4

Alternative USI Usage

The flexible design of the USI allows it to be used for other tasks when serial communication is

not needed. Below are some examples.

14.4.1

Half-Duplex Asynchronous Data Transfer

Using the USI Data Register in three-wire mode it is possible to implement a more compact and

higher performance UART than by software, only.

14.4.2

4-Bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the

counter is clocked externally, both clock edges will increment the counter value.

14.4.3

12-Bit Timer/Counter

Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.

14.4.4

Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt.

The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature

is selected by the USICS1 bit.

14.4.5

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

14.5

14.5.1

USIDR – USI Data Register

The USI Data Register can be accessed directly but a copy of the data can also be found in the

USI Buffer Register.

Depending on the USICS1:0 bits of the USI Control Register a (left) shift operation may be per-

formed. The shift operation can be synchronised to an external clock edge, to a Timer/Counter0

Compare Match, or directly to software via the USICLK bit. If a serial clock occurs at the same

cycle the register is written, the register will contain the value written and no shift is performed.

Note that even when no wire mode is selected (USIWM1:0 = 0) both the external data input

(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.

The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to

the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input

is sampled and data output is changed on opposite clock edges. The latch is open (transparent)

during the first half of a serial clock cycle when an external clock source is selected (USICS1 =

1) and constantly open when an internal clock source is used (USICS1 = 0). The output will be

changed immediately when a new MSB is written as long as the latch is open.

Note that the Data Direction Register bit corresponding to the output pin must be set to one in

order to enable data output from the USI Data Register.

Bit

0x0F (0x2F)

MSB

LSB

USIDR

Read/Write

R/W

Initial Value

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