ATtiny44 datasheet(36/236 Pages) ATMEL

36 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

7.4.3

Brown-out Detector

If the Brown-out Detector is not needed in the application, this module should be turned off. If the

Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes,

and hence, always consume power. In the deeper sleep modes, this will contribute significantly

to the total current consumption. See “Brown-out Detection” on page 41 and “Software BOD Dis-

able” on page 34 for details on how to configure the Brown-out Detector.

7.4.4

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. See “Internal Voltage

Reference” on page 42 for details on the start-up time.

7.4.5

Watchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. See “Watchdog Timer” on page 42 for details on how to configure the Watchdog Timer.

7.4.6

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

both the I/O clock (clk

I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device

will be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. See the section “Digital Input Enable and Sleep Modes” on page 58 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an

analog signal level close to V

CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See

“DIDR0 – Digital Input Disable Register 0” on page 150 for details.

7.5

7.5.1

MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

• Bit 7 – BODS: BOD Sleep

BOD disable functionality is available in some devices, only. See “Limitations” on page 35.

In order to disable BOD during sleep (see Table 7-1 on page 33) the BODS bit must be written to

logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,

Bit

76543210

BODS

PUD

SM1

SM0

BODSE

ISC01

ISC00

MCUCR

Read/Write

R/W

Initial Value

00000000

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