ATtiny44 datasheet(97/236 Pages) ATMEL

97 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

Figure 12-6. CTC Mode, Timing Diagram

An interrupt can be generated at each time the counter value reaches the TOP value by either

using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,

changing the TOP to a value close to BOTTOM when the counter is running with none or a low

prescaler value must be done with care since the CTC mode does not have the double buffering

feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the

counter will miss the compare match. The counter will then have to count to its maximum value

(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many

cases this feature is not desirable. An alternative will then be to use the fast PWM mode using

OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.

For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre-

quency of

A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined

by the following equation:

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

12.8.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared

on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare

Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope

operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor-

rect and phase and frequency correct PWM modes that use dual-slope operation. This high

frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC

TCNTn

OCnA

(Toggle)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

Period

(COMnA1:0 = 1)

OCnA

clk_I/O

2 N

OCRnA

()

⋅⋅

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