ATtiny44 datasheet(33/236 Pages) ATMEL

33 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an

ideal choise for low power applications. In addition, sleep modes enable the application to shut

down unused modules in the MCU, thereby saving power. The AVR provides various sleep

modes allowing the user to tailor the power consumption to the application’s requirements.

7.1

Sleep Modes

Figure 6-1 on page 24 presents the different clock systems and their distribution in

ATtiny24/44/84. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows

the different sleep modes and their wake up sources.

Note:

1. For INT0, only level interrupt.

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which

sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the

SLEEP instruction. See Table 7-2 on page 37 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up the changed level must be held for

some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See

“External Interrupts” on page 49 for details.

7.1.1

Idle Mode

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the

interrupt system to continue operating. This sleep mode basically halts clk

CPU and clkFLASH, while

allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,

Table 7-1.

Active Clock Domains and Wake-up Sources in Different Sleep Modes

Sleep Mode

Active Clock Domains

Oscillators

Wake-up Sources

Idle

ADC Noise Reduction

X(1)

Power-down

X(1)

Stand-by

X(1)

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