UPSD3313D-40U6T datasheet(48/231 Pages) STMICROELECTRONICS

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uPSD33xx

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POWER SAVING MODES

The uPSD33xx is a combination of two die, or

modules, each module having it’s own current

consumption characteristics. This section de-

scribes reduced power modes for the MCU Mod-

ule.

See

the

section,

Power

Management, page 137 for reduced power modes

of the PSD Module. Total current consumption for

the combined modules is determined in the DC

specifications at the end of this document.

The MCU Module has three software-selectable

modes of reduced power operation.

■

Idle Mode

■

Power-down Mode

■

Reduced Frequency Mode

Idle Mode

Idle Mode will halt the 8032 MCU core while leav-

ing the MCU peripherals active (Idle Mode blocks

MCU_CLK only). For lowest current consumption

in this mode, it is recommended to disable all un-

used peripherals, before entering Idle mode (such

as the ADC and the Debug Unit breakpoint com-

parators). The following functions remain fully ac-

tive during Idle Mode (except if disabled by SFR

settings).

■

External Interrupts INT0 and INT1

■

Timer 0, Timer 1 and Timer 2

■

Supervisor reset from: LVD, JTAG Debug,

External RESET_IN_, but not the WTD

■

ADC

■

I2C Interface

■

UART0 and UART1 Interfaces

■

SPI Interface

■

Programmable Counter Array

An interrupt generated by any of these peripher-

als, or a reset generated from the supervisor, will

cause Idle Mode to exit and the 8032 MCU will re-

sume normal operation.

The output state on I/O pins of MCU ports 1, 3, and

4 remain unchanged during Idle Mode.

To enter Idle Mode, the 8032 MCU executes an in-

struction to set the IDL bit in the SFR named

PCON, shown in Table 24., page 50. This is the

last instruction executed in normal operating mode

before Idle Mode is activated. Once in Idle Mode,

the MCU status is entirely preserved, and there

are no changes to: SP, PSW, PC, ACC, SFRs,

DATA, IDATA, or XDATA.

The following are factors related to Idle Mode exit:

–

Activation of any enabled interrupt will cause

the IDL bit to be cleared by hardware,

terminating Idle Mode. The interrupt is

serviced, and following the Return from

Interrupt instruction (RETI), the next

instruction to be executed will be the one

which follows the instruction that set the IDL

bit in the PCON SFR.

–

After a reset from the supervisor, the IDL bit is

cleared, Idle Mode is terminated, and the MCU

restarts after three MCU machine cycles.

Power-down Mode

Power-down Mode will halt the 8032 core and all

MCU peripherals (Power-down Mode blocks

MCU_CLK and PERIPH_CLK). This is the lowest

power state for the MCU Module. When the PSD

Module is also placed in Power-down mode, the

lowest total current consumption for the combined

die is achieved for the uPSD33xx. See Power

Management, page 137 in the PSD Module sec-

tion for details on how to also place the PSD Mod-

ule in Power-down mode. The sequence of 8032

instructions is important when placing both mod-

ules into Power-down Mode.

The instruction that sets the PD Bit in the SFR

named PCON (Table 24., page 50) is the last in-

struction executed prior to the MCU Module going

into Power-down Mode. Once in Power-down

Mode, the on-chip oscillator circuitry and all clocks

are

stopped.

The

SFRs,

DATA,

IDATA,

and XDATA are preserved.

Power-down Mode is terminated only by a reset

from

the

supervisor,

originating

from

the

RESET_IN_ pin, the Low-Voltage Detect circuit

(LVD), or a JTAG Debug reset command. Since

the clock to the WTD is not active during Power-

down mode, it is not possible for the supervisor to

generate a WDT reset.

Table 22., page 49 summarizes the status of I/O

pins and peripherals during Idle and Power-down

Modes on the MCU Module. Table 23., page 49

shows the state of 8032 MCU address, data, and

control signals during these modes.

Reduced Frequency Mode

The 8032 MCU consumes less current when oper-

ating at a lower clock frequency. The MCU can re-

duce it’s own clock frequency at run-time by

writing to three bits, CPUPS[2:0], in the SFR

named CCON0 described in Table 21., page 47.

These bits effectively divide the clock frequency

(fOSC) coming in from the external crystal or oscil-

lator device. The clock division range is from 1/2 to

1/2048, and the resulting frequency is fMCU.

This MCU clock division does not affect any of the

peripherals, except for the WTD. The clock driving

the WTD is the same clock driving the 8032 MCU

core as shown in Figure 14., page 46.

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