UPSD3313D-40U6T datasheet(16/231 Pages) STMICROELECTRONICS

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uPSD33xx

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Internal Memory (MCU Module, Standard 8032

Memory: DATA, IDATA, SFR)

DATA Memory. The first 128 bytes of internal

SRAM ranging from address 0x0000 to 0x007F

are called DATA, which can be accessed using

8032 direct or indirect addressing schemes and

are typically used to store variables and stack.

Four register banks, each with 8 registers (R0 –

R7), occupy addresses 0x0000 to 0x001F. Only

one of these four banks may be enabled at a time.

The next 16 locations at 0x0020 to 0x002F contain

128 directly addressable bit locations that can be

used as software flags. SRAM locations 0x0030

and above may be used for variables and stack.

IDATA Memory. The next 128 bytes of internal

SRAM are named IDATA and range from address

0x0080 to 0x00FF. IDATA can be accessed only

through 8032 indirect addressing and is typically

used to hold the MCU stack as well as data vari-

ables. The stack can reside in both DATA and

IDATA memories and reach a size limited only by

the available space in the combined 256 bytes of

these two memories (since stack accesses are al-

ways done using indirect addressing, the bound-

ary between DATA and IDATA does not exist with

regard to the stack).

SFR Memory. Special Function Registers (Table

5., page 24) occupy a separate physical memory,

but they logically overlap the same 128 bytes as

IDATA, ranging from address 0x0080 to 0x00FF.

SFRs are accessed only using direct addressing.

There 86 active registers used for many functions:

changing the operating mode of the 8032 MCU

core, controlling 8032 peripherals, controlling I/O,

and managing interrupt functions. The remaining

unused SFRs are reserved and should not be ac-

cessed.

16 of the SFRs are both byte- and bit-addressable.

Bit-addressable SFRs are those whose address

ends in “0” or “8” hex.

External Memory (PSD Module: Program

memory, Data memory)

The PSD Module has four memories: main Flash,

secondary Flash, SRAM, and CSIOP. See the

PSD MODULE section for more detailed informa-

tion on these memories.

Memory mapping in the PSD Module is imple-

mented with the Decode PLD (DPLD) and option-

ally the Page Register. The user specifies decode

equations for individual segments of each of the

memories using the software tool PSDsoft Ex-

press. This is a very easy point-and-click process

allowing total flexibility in mapping memories. Ad-

ditionally, each of the memories may be placed in

various combinations of 8032 program address

space or 8032 data address space by using the

software tool PSDsoft Express.

Program Memory. External program memory is

addressed by the 8032 using its 16-bit Program

Counter (PC) and is accessed with the 8032 sig-

nal, PSEN. Program memory can be present at

any address in program space between 0x0000

and 0xFFFF.

After a power-up or reset, the 8032 begins pro-

gram execution from location 0x0000 where the

reset vector is stored, causing a jump to an initial-

ization routine in firmware. At address 0x0003, just

following the reset vector are the interrupt service

locations. Each interrupt is assigned a fixed inter-

rupt service location in program memory. An inter-

rupt causes the 8032 to jump to that service

location, where it commences execution of the

service routine. External Interrupt 0 (EXINT0), for

example, is assigned to service location 0x0003. If

EXINT0 is going to be used, its service routine

must begin at location 0x0003. Interrupt service lo-

cations are spaced at 8-byte intervals: 0x0003 for

EXINT0, 0x000B for Timer 0, 0x0013 for EXINT1,

and so forth. If an interrupt service routine is short

enough, it can reside entirely within the 8-byte in-

terval. Longer service routines can use a jump in-

struction to somewhere else in program memory.

Data Memory. External data is referred to as

XDATA and is addressed by the 8032 using Indi-

rect Addressing via its 16-bit Data Pointer Register

(DPTR) and is accessed by the 8032 signals, RD

and WR. XDATA can be present at any address in

data space between 0x0000 and 0xFFFF.

Note: the uPSD33xx has dual data pointers

(source and destination) making XDATA transfers

much more efficient.

Memory Placement. PSD Module architecture

allows the placement of its external memories into

different combinations of program memory and

data memory spaces. This means the main Flash,

the secondary Flash, and the SRAM can be

viewed by the 8032 MCU in various combinations

of program memory or data memory as defined by

PSDsoft Express.

As an example of this flexibility, for applications

that require a great deal of Flash memory in data

space (large lookup tables or extended data re-

cording), the larger main Flash memory can be

placed in data space and the smaller secondary

Flash memory can be placed in program space.

The opposite can be realized for a different appli-

cation if more Flash memory is needed for code

and less Flash memory for data.

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