UPSD3313D-40U6T datasheet(98/231 Pages) STMICROELECTRONICS

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uPSD33xx

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Operating Modes

The I2C interface supports four operating modes:

■

Master-Transmitter

■

Master-Receiver

■

Slave-Transmitter

■

Slave-Receiver

The interface may operate as either a Master or a

Slave within a given application, controlled by firm-

ware writing to SFRs.

By default after a reset, the I2C interface is in Mas-

ter Receiver mode, and the SDA/P3.6 and SCL/

P3.7 pins default to GPIO input mode, high imped-

ance, so there is no I2C bus interference. Before

using the I2C interface, it must be initialized by

firmware, and the pins must be configured. This is

discussed in I2C Operating Sequences, page 108.

Bus Arbitration

A Master device always samples the I2C bus to

ensure a bus line is high whenever that Master is

asserting a logic 1. If the line is low at that time, the

Master recognizes another device is overriding it’s

own transmission.

A Master may start a transfer only if the I2C bus is

not busy. However, it’s possible that two or more

Masters may generate a START condition simulta-

neously. In this case, arbitration takes place on the

SDA line each time SCL is high. The Master that

first senses that its bus sample does not corre-

spond to what it is driving (SDA line is low while it’s

asserting a high) will immediately change from

Master-Transmitter to Slave-Receiver mode. The

arbitration process can carry on for many bit times

if both Masters are addressing the same Slave de-

vice, and will continue into the data bits if both

Masters are trying to be Master-Transmitter. It is

also possible for arbitration to carry on into the ac-

knowledge bits if both Masters are trying to be

Master-Receiver. Because address and data in-

formation on the bus is determined by the winning

Master, no information is lost during the arbitration

process.

Clock Synchronization

Clock synchronization is used to synchronize arbi-

trating Masters, or used as a handshake by a de-

vices to slow down the data transfer.

Clock Sync During Arbitration. During bus ar-

bitration between competing Masters, Master_X,

with the longest low period on SCL, will force

Master_Y to wait until Master_X finishes its low

period before Master_Y proceeds to assert its high

period on SCL. At this point, both Masters begin

asserting their high period on SCL simultaneously,

and the Master with the shortest high period will be

the first to drive SCL for the next low period. In this

scheme, the Master with the longest low SCL pe-

riod paces low times, and the Master with the

shortest high SCL period paces the high times,

making synchronized arbitration possible.

Clock Sync During Handshaking. This

allows

receivers in different devices to handle various

transfer rates, either at the byte-level, or bit-level.

At the byte-level, a device may pause the transfer

between bytes by holding SCL low to have time to

store the latest received byte or fetch the next byte

to transmit.

At the bit-level, a Slave device may extend the low

period of SCL by holding it low. Thus the speed of

any Master device will adapt to the internal opera-

tion of the Slave.

General Call Address

A General Call (GC) occurs when a Master-Trans-

mitter initiates a transfer containing a Slave ad-

dress of 0000000b, and the R/W bit is logic 0. All

Slave devices capable of responding to this broad-

cast message will acknowledge the GC simulta-

neously and then behave as a Slave-Receiver.

The next byte transmitted by the Master will be ac-

cepted and acknowledged by all Slaves capable of

handling the special data bytes. A Slave that can-

not handle one of these data bytes must ignore it

by not acknowledging it. The I2C specification lists

the possible meanings of the special bytes that fol-

low the first GC address byte, and the actions to

be taken by the Slave device(s) upon receiving

them. A common use of the GC by a Master is to

dynamically assign device addresses to Slave de-

vices on the bus capable of a programmable de-

vice address.

The uPSD33xx can generate a GC as a Master-

Transmitter, and it can receive a GC as a Slave.

When receiving a GC address (00h), an interrupt

will be generated so firmware may respond to the

special GC data bytes if desired.

UPSD3313D-40U6T Datasheet(PDF) 98 Page - STMicroelectronics

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