| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
UPSD3313D-40U6T Datasheet(PDF) 47 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
UPSD3313D-40U6T Datasheet(HTML) 47 Page - STMicroelectronics |
|
47 / 231 page ![]() 47/231 uPSD33xx Table 21. CCON0: Clock Control Register (SFR F9h, reset value 10h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – DBGCE CPUAR CPUPS[2:0] Details Bit Symbol R/W Definition 7–– Reserved 6–– Reserved 5–– Reserved 4DBGCE R,W Debug Unit Breakpoint Comparator Enable 0 = JTAG Debug Unit comparators are disabled 1 = JTAG Debug Unit comparators are enabled (Default condition after reset) 3 CPUAR R,W Automatic MCU Clock Recovery 0 = There is no change of CPUPS[2:0] when an interrupt occurs. 1 = Contents of CPUPS[2:0] automatically become 000b whenever any interrupt occurs. 2:0 CPUPS R,W MCUCLK Pre-Scaler 000b: fMCU = fOSC (Default after reset) 001b: fMCU = fOSC/2 010b: fMCU = fOSC/4 011b: fMCU = fOSC/8 100b: fMCU = fOSC/16 101b: fMCU = fOSC/32 110b: fMCU = fOSC/1024 111b: fMCU = fOSC/2048 |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |