UPSD3313D-40U6T datasheet(43/231 Pages) STMICROELECTRONICS

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uPSD33xx

Individual Interrupt Sources

External Interrupts Int0 and Int1. External

in-

terrupt inputs on pins EXTINT0 and EXTINT1

(pins 3.2 and 3.3) are either edge-triggered or lev-

el-triggered, depending on bits IT0 and IT1 in the

SFR named TCON.

When an external interrupt is generated from an

edge-triggered (falling-edge) source, the appropri-

ate flag bit (IE0 or IE1) is automatically cleared by

hardware upon entering the ISR.

When an external interrupt is generated from a

level-triggered (low-level) source, the appropriate

flag bit (IE0 or IE1) is NOT automatically cleared

by hardware.

Timer 0 and 1 Overflow Interrupt. Timer 0 and

Timer 1 interrupts are generated by the flag bits

TF0 and TF1 when there is an overflow condition

in the respective Timer/Counter register (except

for Timer 0 in Mode 3).

Timer 2 Overflow Interrupt. This

interrupt

generated to the MCU by a logical OR of flag bits,

TF2 and EXE2. The ISR must read the flag bits to

determine the cause of the interrupt.

–

TF2 is set by an overflow of Timer 2.

–

EXE2 is generated by the falling edge of a

signal on the external pin, T2X (pin P1.1).

UART0 and UART1 Interrupt. Each

the

UARTs have identical interrupt structure. For each

UART, a single interrupt is generated to the MCU

by the logical OR of the flag bits, RI (byte received)

and TI (byte transmitted).

The ISR must read flag bits in the SFR named

SCON0 for UART0, or SCON1 for UART1 to de-

termine the cause of the interrupt.

SPI Interrupt. The SPI interrupt has four interrupt

sources, which are logically ORed together when

interrupting the MCU. The ISR must read the flag

bits to determine the cause of the interrupt.

A flag bit is set for: end of data transmit (TEISF);

data receive overrun (RORISF); transmit buffer

empty (TISF); or receive buffer full (RISF).

I2C Interrupt. The flag bit INTR is set by a variety

of conditions occurring on the I2C interface: re-

ceived own slave address (ADDR flag); received

general call address (GC flag); received STOP

condition (STOP flag); or successful transmission

or reception of a data byte.The ISR must read the

flag bits to determine the cause of the interrupt.

ADC Interrupt. The flag bit AINTF is set when an

A-to-D conversion has completed.

PCA Interrupt. The PCA has eight interrupt

sources, which are logically ORed together when

interrupting the MCU.The ISR must read the flag

bits to determine the cause of the interrupt.

–

Each of the six TCMs can generate a "match

or capture" interrupt on flag bits OFV5..0

respectively.

–

Each of the two 16-bit counters can generate

an overflow interrupt on flag bits INTF1 and

INTF0 respectively.

Tables 17 through Table 20., page 45 have de-

tailed bit definitions of the interrupt system SFRs.

Table 17. IE: Interrupt Enable Register (SFR A8h, reset value 00h)

Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

ET2

ES0

ET1

EX1

ET0

EX0

Details

Bit

Symbol

R/W

Function

7EA

R,W

Global disable bit. 0 = All interrupts are disabled. 1 = Each interrupt

source can be individually enabled or disabled by setting or clearing its

enable bit.

6–

R,W

Do not modify this bit. It is used by the JTAG debugger for instruction

tracing. Always read the bit and write back the same bit value when

writing this SFR.

5(1)

ET2

R,W

Enable Timer 2 Interrupt

4(1)

ES0

R,W

Enable UART0 Interrupt

3(1)

ET1

R,W

Enable Timer 1 Interrupt

2(1)

EX1

R,W

Enable External Interrupt INT1

1(1)

ET0

R,W

Enable Timer 0 Interrupt

0(1)

EX0

R,W

Enable External Interrupt INT0

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