UPSD3313D-40U6T datasheet(67/231 Pages) STMICROELECTRONICS

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uPSD33xx

The formula to determine WDT time-out period is:

WDTPERIOD = tMACH_CYC x NOVERFLOW

NOVERFLOW is the number of WDT up-counts re-

quired to reach FFFFFFh. This is determined by

the value written to the SFR, WDRST.

tMACH_CYC is the average duration of one MCU

machine cycle. By default, an MCU machine cycle

is always 4 MCU_CLK periods for uPSD33xx, but

the following factors can sometimes add more

MCU_CLK periods per machine cycle:

–

The number of MCU_CLK periods assigned to

MCU memory bus cycles as determined in the

SFR, BUSCON. If this setting is greater than

4, then machine cycles have additional

MCU_CLK periods during memory transfers.

–

Whether or not the PFQ/BC circuitry issues a

stall during a particular MCU machine cycle. A

stall adds more MCU_CLK periods to a

machine cycle until the stall is removed.

tMACH_CYC is also affected by the absolute time of

a single MCU_CLK period. This number is fixed by

the following factors:

–

Frequency of the external crystal, resonator,

or oscillator: (fOSC)

–

Bit settings in the SFR CCON0, which can

divide fOSC and change MCU_CLK

As an example, assume the following:

fOSC is 40MHz, thus its period is 25ns.

CCON0 is 10h, meaning no clock division, so

the period of MCU_CLK is also 25ns.

BUSCON is C1h, meaning the PFQ and BC

are enabled, and each MCU memory bus

cycle is 4 MCU_CLK periods, adding no

additional MCU_CLK periods to MCU

machine cycles during memory transfers.

Assume there are no stalls from the PFQ/BC.

In reality, there are occational stalls but their

occurance has minimal impact on WDT

timeout period.

WDRST contains 00h, meaning a full 224 up-

counts are required to reach FFFFFh and

generate a reset.

In this example,

tMACH_CYC = 100ns (4 MCU_CLK periods x 25ns)

NOVERFLOW = 2

24 = 16777216 up-counts

WDTPERIOD = 100ns X 16777216 = 1.67 seconds

The actual value will be slightly longer due to PFQ/

BC.

Firmware Example: The following 8051 assem-

bly code illustrates how to operate the WDT. A

simple statement in the reset initialization firmware

enables the WDT, and then a periodic write to

clear the WDT in the main firmware is required to

keep the WDT from overflowing. This firmware is

based on the example above (40MHz fOSC,

CCON0 = 10h, BUSCON = C1h).

For example, in the reset initialization firmware

(the function that executes after a jump to the reset

vector):

Somewhere in the flow of the main program, this

statement will execute periodically to reset the

WDT before it’s time-out period of 1.67 seconds.

For example:

MOV AE, #AA

; enable WDT by writing value to

; WDKEY other than 55h

MOV A6, #00

; reset WDT, loading 000000h.

; Counting will automatically

; resume as long as 55h in not in

; WDKEY

UPSD3313D-40U6T Datasheet(PDF) 67 Page - STMicroelectronics

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