UPSD3313D-40U6T datasheet(96/231 Pages) STMICROELECTRONICS

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Communication Flow

I2C data flow control is based on the fact that all

I2C compatible devices will drive the bus lines with

open-drain (or open-collector) line drivers pulled

up with external resistors, creating a wired-AND

situation. This means that either bus line (SDA or

SCL) will be at a logic '1' level only when no I2C de-

vice is actively driving the line to logic '0.' The logic

for handshaking, arbitration, synchronization, and

collision detection is implemented by each I2C de-

vice having:

The ability to hold a line low against the will of

the other devices who are trying to assert the

line high.

The ability of a device to detect that another

device is driving the line low against its will.

Assert high means the driver releases the line and

external pull-ups passively raise the signal to logic

'1.' Holding low means the open-drain driver is

actively pulling the signal to ground for a logic '0.'

For example, if a Slave device cannot transmit or

receive a byte because it is distracted by and inter-

rupt or it has to wait for some process to complete,

it can hold the SCL clock line low. Even though the

Master device is generating the SCL clock, the

Master will sense that the Slave is holding the SCL

line low against the will of the Master, indicating

that the Master must wait until the Slave releases

SCL before proceeding with the transfer.

Another example is when two Master devices try

to put information on the bus simultaneously, the

first one to release the SDA data line looses arbi-

tration while the winner continues to hold SDA low.

Two types of data transfers are possible with I2C

depending

the

R/W

bit,

see

Figure

39., page 97.

Data transfer from Master Transmitter to

Slave Receiver (R/W = 0). In this case, the

Master generates a START condition on the

bus and it generates a clock signal on the SCL

line. Then the Master transmits the first byte

on the SDA line containing the 7-bit Slave

address plus the R/W bit. The Slave who owns

that address will respond with an acknowledge

bit on SDA, and all other Slave devices will not

respond. Next, the Master will transmit a data

byte (or bytes) that the addressed Slave must

receive. The Slave will return an acknowledge

bit after each data byte it successfully

receives. After the final byte is transmitted by

the Master, the Master will generate a STOP

condition on the bus, or it will generate a RE-

START conditon and begin the next transfer.

There is no limit to the number of bytes that

can be transmitted during a transfer session.

Data transfer from Slave Transmitter to

Master Receiver (R/W = 1). In this case, the

Master generates a START condition on the

bus and it generates a clock signal on the SCL

line. Then the Master transmits the first byte

on the SDA line containing the 7-bit Slave

address plus the R/W bit. The Slave who owns

that address will respond with an acknowledge

bit on SDA, and all other Slave devices will not

respond. Next, the addressed Slave will

transmit a data byte (or bytes) to the Master.

The Master will return an acknowledge bit

after each data byte it successfully receives,

unless it is the last byte the Master desires. If

so, the Master will not acknowledge the last

byte and from this, the Slave knows to stop

transmitting data bytes to the Master. The

Master will then generate a STOP condition on

the bus, or it will generate a RE-START

conditon and begin the next transfer. There is

no limit to the number of bytes that can be

transmitted during a transfer session.

A few things to know related to these transfers:

–

Either the Master or Slave device can hold the

SCL clock line low to indicate it needs more

time to handle a byte transfer. An indefinite

holding period is possible.

–

A START condition is generated by a Master

and recognized by a Slave when SDA has a 1-

to-0 transition while SCL is high (Figure

39., page 97).

–

A STOP condition is generated by a Master

and recognized by a Slave when SDA has a 0-

to1 transition while SCL is high (Figure

39., page 97).

–

A RE-START (repeated START) condition

generated by a Master can have the same

function as a STOP condition when starting

another data transfer immediately following

the previous data transfer (Figure

39., page 97).

–

When transferring data, the logic level on the

SDA line must remain stable while SCL is

high, and SDA can change only while SCL is

low. However, when not transferring data,

SDA may change state while SCL is high,

which creates the START and STOP bus

conditions.

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