UPSD3313D-40U6T datasheet(75/231 Pages) STMICROELECTRONICS

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uPSD33xx

Table 41. T2CON: Timer 2 Control Register (SFR C8h, reset value 00h)

Note: 1. The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact same function as RCLK and TCLK.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Details

Bit

Symbol

R/W

Definition

TF2

R,W

Timer 2 flag, causes interrupt if enabled.

TF2 is set by hardware upon overflow. Must be cleared by firmware. TF2

will not be set when either RCLK or TCLK =1.

EXF2

R,W

Timer 2 flag, causes interrupt if enabled.

EXF2 is set when a capture or reload is caused by a negative transition

on T2X pin and EXEN2 = 1. EXF2 must be cleared by firmware.

RCLK(1)

R,W

UART0 Receive Clock control.

When RCLK = 1, UART0 uses Timer 2 overflow pulses for its receive

clock in Modes 1 and 3. RCLK=0, Timer 1 overflow is used for its receive

clock

TCLK(1)

R,W

UART0 Transmit Clock control.

When TCLK = 1, UART0 uses Timer 2 overflow pulses for its transmit

clock in Modes 1 and 3. TCLK=0, Timer 1 overflow is used for transmit

clock

EXEN2

R,W

Timer 2 External Enable.

When EXEN2 = 1, capture or reload results when negative edge on pin

T2X occurs. EXEN2 = 0 causes Timer 2 to ignore events at pin T2X.

TR2

R,W

Timer 2 run control.

1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off.

1C/T2

R,W

Counter or Timer function select.

When C/T2 = 0, function is timer, clocked by internal clock. When C/T2 =

1, function is counter, clocked by signal sampled on external pin, T2.

0CP/RL2

R,W

Capture/Reload.

When CP/RL2 = 1, capture occurs on negative transition at pin T2X if

EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs when Timer 2

overflows, or on negative transition at pin T2X when EXEN2=1. When

RCLK = 1 or TCLK = 1, CP/RL2 is ignored, and Timer 2 is forced to auto-

reload upon Timer 2 overflow

UPSD3313D-40U6T Datasheet(PDF) 75 Page - STMicroelectronics

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