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ATtiny44 Datasheet(PDF) 149 Page - ATMEL Corporation |
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ATtiny44 Datasheet(HTML) 149 Page - ATMEL Corporation |
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149 / 236 page  149 8006H–AVR–10/09 ATtiny24/44/84 16.13.3 ADCL and ADCH – ADC Data Register 16.13.3.1 ADLAR = 0 16.13.3.2 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 143. 16.13.4 ADCSRB – ADC Control and Status Register B • Bits 7 – BIN: Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. Bit 151413121110 9 8 0x05 (0x25) – – – – – – ADC9 ADC8 ADCH 0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 765 43 21 0 Read/Write RR RR RR R R RR RR RR R R Initial Value 0 0 0 0 0 0 0 0 000 00 00 0 Bit 151413121110 9 8 0x05 (0x25) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH 0x04 (0x24) ADC1 ADC0 – – – – – – ADCL 765 43 21 0 Read/Write RR RR RR R R RR RR RR R R Initial Value 0 0 0 0 0 0 0 0 000 00 00 0 Bit 7 6543 210 0x03 (0x23) BIN ACME – ADLAR – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0000 000 |
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