ATtiny44 datasheet(137/236 Pages) ATMEL

No. de pieza	ATtiny44

Descripción Electrónicos	8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash

PDF	236 Pages

Scroll/Zoom	100%

Fabricante Electrónico	ATMEL [ATMEL Corporation]

Página de inicio	http://www.atmel.com

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137 / 236 page

137

8006H–AVR–10/09

ATtiny24/44/84

When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in

Figure 16-6 below. This assures a fixed delay from the trigger event to the start of conversion. In

this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the

trigger source signal. Three additional CPU clock cycles are used for synchronization logic.

Figure 16-6. ADC Timing Diagram, Auto Triggered Conversion

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. See Figure 16-7.

Figure 16-7. ADC Timing Diagram, Free Running Conversion

Sign and MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Sample & Hold

MUX and REFS

Update

ATtiny44 Datasheet(PDF) 137 Page - ATMEL Corporation

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