ATtiny44 datasheet(113/236 Pages) ATMEL

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113

8006H–AVR–10/09

ATtiny24/44/84

12.11.7

ICR1H and ICR1L – Input Capture Register 1

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit

registers. “Accessing 16-bit Registers” on page 105.

12.11.8

TIMSK1 – Timer/Counter Interrupt Mask Register 1

• Bit 7,6,4,3 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when the register is written.

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Countern Input Capture interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the

ICF1 Flag, located in TIFR1, is set.

• Bit 2– OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 48) is executed when the OCF1B flag, located in

TIFR1, is set.

• Bit 1– OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 48) is executed when the OCF1A flag, located in

TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(see “Interrupts” on page 48) is executed when the TOV1 flag, located in TIFR1, is set.

Bit

765

432

0x25 (0x45)

ICR1[15:8]

ICR1H

0x24 (0x44)

ICR1[7:0]

ICR1L

Read/Write

R/W

Initial Value

Bit

0x0C (0x2C)

–

ICIE1

–

OCIE1B

OCIE1A

TOIE1

TIMSK1

Read/Write

R/W

Initial Value

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