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LP8733-Q1 Datasheet(PDF) 13 Page - Texas Instruments

No. de pieza LP8733-Q1
Descripción Electrónicos  LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator
PDF  86 Pages
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Fabricante Electrónico  TI2 [Texas Instruments]
Página de inicio  https://www.ti.com
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LP8733-Q1 Datasheet(HTML) 13 Page - Texas Instruments

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6.6 I2C Serial Bus Timing Parameters (continued)
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V (see (1)). See Figure 6-1 for details about
the I2C-Compatible Timing diagram.
MIN
MAX
UNIT
trDA
Rise time of SDA signal
Standard mode
1000
ns
Fast mode
20
300
Fast mode+
120
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
20
160
tfDA
Fall time of SDA signal
Standard mode
300
ns
Fast mode
20 × (VDD / 5.5
V)
300
Fast mode+
20 × (VDD / 5.5
V)
120
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
30
160
trCL
Rise time of SCL signal
Standard mode
1000
ns
Fast mode
20
300
Fast mode+
120
High-speed mode, Cb = 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
trCL1
Rise time of SCL signal
after a repeated start
condition and after an
acknowledge bit
High-speed mode, Cb = 100 pF
10
80
ns
High-speed mode, Cb = 400 pF
20
160
tfCL
Fall time of a SCL signal
Standard mode
300
ns
Fast mode
20 × (VDD / 5.5
V)
300
Fast mode+
20 × (VDD / 5.5
V)
120
High-speed mode, Cb = 10 – 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
Cb
Capacitive load for each
bus line (SCL and SDA)
400
pF
tSP
Pulse width of spike
suppressed (SCL and
SDA spikes that are less
then the indicated width
are suppressed)
Standard mode, fast mode, and fast mode+
50
ns
High-speed mode
10
(1)
Cb refers to the capacitance of one bus line.
www.ti.com
LP8733-Q1
SNVSB64A – JUNE 2019 – REVISED JUNE 2021
Copyright © 2022 Texas Instruments Incorporated
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