LP8733-Q1 datasheet(31/86 Pages) TI2

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V(VANA)

VANA_UVLO

State Shutdown

Read

OTP

Standby

PGOOD pin

EN pin

VOUT (Buck1)

VOUT (LDO0)

Buck1 internal powergood

LDO0 internal powergood

Active

800 µs Timer

Buck internal enable

800 µs Timer

LDO0 internal enable

4 ms

2 ms

Clear fault

Figure 7-10. PGOOD Pin Operation in Gated Mode

7.3.8.1.2 PGOOD Pin Continuous Mode

The continuous (or invalid) mode of operation is selected by setting the PGOOD_MODE bit to 1 in the

PGOOD_CTRL_2 register.

For the continuous mode of operation, PGOOD behaves as follows:

• PGOOD is set to active or asserted state upon exiting OTP configuration.

• PGOOD is set to inactive or de-asserted as soon as the regulator is enabled.

• PGOOD status begins indicating output voltage regulation status immediately and continuously.

• During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or

de-asserted while output voltages are outside of regulation ranges and active or asserted when inside of

regulation ranges.

The PG_FAULT register bits are latched, and maintain the fault information until the host clears the fault bit by

writing 1 to the bit. The PGOOD signal also indicates a thermal shutdown and input overvoltage interrupts, which

are cleared by clearing the interrupt bits.

When the regulator voltage is transitioning from one target voltage to another, the PGOOD signal becomes

inactive.

7.3.8.1.3 PGOOD Pin Inactive Mode

When the PGOOD signal becomes inactive, the source for the fault can be read from the PG_FAULT register.

If the invalid output voltage becomes valid again, then the PGOOD signal becomes active. Thus the PGOOD

signal always shows if the monitored output voltages are valid. The block diagram for this operation is shown in

Figure 7-11 and an example of operation is shown in Figure 7-12.

The PGOOD signal can also be configured so that it maintains an inactive state even when the monitored

outputs are valid, but there are PG_FAULT_x bits in the PG_FAULT register pending clearance. This type of

operation is selected by setting the PGFAULT_GATES_PGOOD bit to 1 in the PGOOD_CTRL_2 register.

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LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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