LP8733-Q1 datasheet(23/86 Pages) TI2

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7.3.5 Regulator Control

7.3.5.1 Enabling and Disabling Regulators

The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable

and disable the buck regulators:

• Using the BUCKx_EN bit in the BUCKx_CTRL_1 register (the BUCKx_EN_PIN_CTRL bit is 0 in the

BUCKx_CTRL_1 register).

• Using the EN control pin (the BUCKx_EN bit and the BUCKx_EN_PIN_CTRL bit is 1).

Similarly, there are two ways to enable and disable the LDO regulators:

• Using the LDOx_EN bit in the LDOx_CTRL register (the LDOx_EN_PIN_CTRL bit is 0 in the LDOx_CTRL

• Using the EN control pin (the LDOx_EN bit is 1 and the LDOx_EN_PIN_CTRL bit is 1).

If the EN control pin is used for enable and disable, then the following occurs:

• The delay from the control signal rising edge to start-up is set by the BUCKx_STARTUP_DELAY[3:0] bits in

the BUCKx_DELAY register and the LDOx_STARTUP_DELAY[3:0] bits in the LDOx_DELAY register.

• The delay from the control signal falling edge to shutdown is set by the BUCKx_SHUTDOWN_DELAY[3:0]

bits in the BUCKx_DELAY register and the LDOx_SHUTDOWN_DELAY[3:0] bits in the LDOx_DELAY

The delays are only valid for the EN signal transitions and not for control with I2C writings to the BUCKx_EN and

the LDOx_EN bits.

The control of the regulator (with 0-ms delays) is shown in Table 7-3. Dual-phase regulator is controlled with

registers of the master phase.

Table 7-3. Regulator Control

BUCKx_EN AND

LDOx_EN

BUCKx_EN_PIN_CTRL AND

LDOx_EN_PIN_CTRL

EN PIN

BUCKx OUTPUT VOLTAGE AND

LDOx OUTPUT VOLTAGE

Enable and disable control

with the BUCKx_EN and the

LDOx_EN bit

Don't Care

Disabled

Don't Care

BUCKx_VSET[7:0] and LDOx_VSET[4:0]

Enable and disable control

with the EN pin

Low

Disabled

High

BUCKx_VSET[7:0] and LDOx_VSET[4:0]

The buck regulator is enabled by the EN pin or by I2C writing, as shown in Figure 7-6. The soft-start circuit

limits the in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage

becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase

above the 0.35-V level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum

of 1 ms), then the regulator is disabled, and the BUCKx_SC_INT interrupt in the INT_BUCK register is set.

When the output voltage reaches the the Power-Good threshold level, the BUCKx_PG_INT interrupt flag in

the INT_BUCK register is set. The Power-Good interrupt flag, when reaching the valid output voltage, can be

masked using the BUCKx_PGR_MASK bit in the BUCK_MASK register. The Power-Good interrupt flag can also

be generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection

is set by the BUCKx_PGF_MASK bit in the BUCK_MASK register. A BUCKx_PG_STAT bit in the BUCK_STAT

A PGOOD_WINDOW_BUCK bit in the PGOOD_CTRL_1 register sets the detection method for the valid buck

output voltage, either under-voltage detection, or under-voltage and over-voltage detection.

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LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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