LP8733-Q1 datasheet(75/86 Pages) TI2

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10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP8733xx-Q1 make the choice of layout important. Good

power supply results only occur when care is given to proper design and layout. Layout affects noise pickup

and generation and can cause a good design to perform with less-than-expected results. With a range of output

currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB

design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and

current regulation across its intended operating voltage and current range.

1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and

thick to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pins

of LP8733xx-Q1, as well as the trace between the negative node of the input capacitor and the power

PGND_Bx pins, must be kept as short as possible. The input capacitance provides a low-impedance voltage

source for the switching converter. The inductance of the connection is the most important parameter of a

local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for

proper device operation. The parasitic inductance can be reduced by using a ground plane as close as

possible to the top layer by using thin dielectric layer between the top layer and the ground plane.

2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output

voltage. The output filter must be placed as close as possible to the device, keeping the switch node small

for best EMI behavior. Route the traces between the output capacitors of the LP8733xx-Q1 and the input

capacitors of the load direct and wide to avoid losses due to the IR drop.

3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a

quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling

capacitor as close as possible to the VANA pin.

4. If remote voltage sensing can be used for the load, connect the LP8733xx-Q1 feedback pins FB_Bx to the

respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept

away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such

as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and

close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground

plane if possible. If series resistors are used for load current measurement, place them after connection of

the voltage feedback.

5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers

which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.

6. LDO performance (PSRR, noise, and transient response) depend on the layout of the PCB. Best

performance is achieved by placing CIN and COUT as close to the LP8733xx-Q1 device as practical.

The ground connections for CIN and COUT must be back to the LP8733xx-Q1 AGND with as wide

and as short of a copper trace as is practical and with multiple vias if routing is done on other layer.

Avoid connections using long trace lengths, narrow trace widths, or connection through small via. These

add parasitic inductances and resistance that results in inferior performance, especially during transient

conditions.

Due to the small package of this converter and the overall small solution size, the thermal performance of the

PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and

convection surfaces, and the presence of other heat-generating components affect the power dissipation limits

of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.

Wide power traces can sink dissipated heat. This can be improved further on multi-layer PCB designs with

vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal

resistances, thereby reducing the device junction temperature, TJ. TI strongly recommends performance of a

careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process by using a

thermal modeling analysis software.

www.ti.com

LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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