LP8733-Q1 datasheet(54/86 Pages) TI2

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Table 7-59. INT_TOP_1 Register Field Descriptions (continued)

Bits

Field

Type

Default

Description

LDO_INT

Interrupt indicating that the LDO1 and LDO0 have a pending interrupt. The reason for

the interrupt is indicated in the INT_LDO register.

This bit is cleared automatically when the INT_LDO register is cleared to 0x00.

BUCK_INT

Interrupt indicating that the Buck1 and Buck0 have a pending interrupt. The reason

for the interrupt is indicated in the INT_BUCK register.

This bit is cleared automatically when INT_BUCK register is cleared to 0x00.

SYNC_CLK_INT

R/W

Latched status bit indicating that the external clock has appeared or disappeared.

Write 1 to clear interrupt.

TDIE_SD_INT

R/W

Latched status bit indicating that the die junction temperature has exceeded the

thermal shutdown level. The regulators have been disabled if they were enabled

and the GPO and GPO2 signals are driven low. The regulators cannot be enabled

if this bit is active. The actual status of the thermal shutdown is indicated by the

TDIE_SD_STAT bit in the TOP_STAT register.

Write 1 to clear interrupt.

TDIE_WARN_INT

R/W

Latched status bit indicating that the die junction temperature has exceeded the

thermal warning level. The actual status of the thermal warning is indicated by the

TDIE_WARN_STAT bit in the TOP_STAT register.

Write 1 to clear interrupt.

OVP_INT

R/W

Latched status bit indicating that the input voltage has exceeded the over-voltage

detection level. The regulators have been disabled if they were enabled and the GPO

and GPO2 signals are driven low. The actual status of the over-voltage is indicated by

the OVP_STAT bit in the TOP_STAT register.

Write 1 to clear interrupt.

I_MEAS_INT

R/W

Latched status bit indicating that the load current measurement result is available in

the I_LOAD_1 and I_LOAD_2 registers.

Write 1 to clear interrupt.

7.6.1.27 INT_TOP_2

INT_TOP_2 is shown in Table 7-61, Address: 0x1A

Table 7-60. INT_TOP_2 Register

Reserved - do not use

RESET_REG_I

Table 7-61. INT_TOP_2 Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R/W

000 0000

RESET_REG_INT

R/W

Latched status bit indicating that either VANA supply voltage has been below the

undervoltage threshold level or the host has requested a reset using the SW_RESET

bit in RESET register. The regulators have been disabled, the registers are reset to

the default values, and the normal startup procedure is done.

Write 1 to clear interrupt.

7.6.1.28 INT_BUCK

INT_BUCK is shown in Table 7-63, Address: 0x1B

Table 7-62. INT_BUCK Register

Reserved - do

not use

BUCK1_PG

_INT

BUCK1_SC

_INT

BUCK1_ILIM

_INT

Reserved - do

not use

BUCK0_PG

_INT

BUCK0_SC

_INT

BUCK0_ILIM

_INT

LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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