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LP8733-Q1 Datasheet(PDF) 57 Page - Texas Instruments |
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LP8733-Q1 Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 86 page  Table 7-69. BUCK_STAT Register Field Descriptions (continued) Bits Field Type Default Description 0 BUCK0_ILIM _STAT R 0 Status bit indicating the Buck0 current limit status (raw status): 0 - Buck0 output current is below the current limit level. 1 - Buck0 output current limit is active. 7.6.1.32 LDO_STAT LDO_STAT is shown in Table 7-71, Address: 0x1F Table 7-70. LDO_STAT Register D7 D6 D5 D4 D3 D2 D1 D0 LDO1_STAT LDO1_PG _STAT Reserved - do not use LDO1_ILIM _STAT LDO0_STAT LDO0_PG _STAT Reserved - do not use LDO0_ILIM _STAT Table 7-71. LDO_STAT Register Field Descriptions Bits Field Type Default Description 7 LDO1_STAT R 0 Status bit indicating the enable and disable status of the LDO1: 0 - LDO1 regulator is disabled. 1 - LDO1 regulator is enabled. 6 LDO1_PG_STAT R 0 Status bit indicating the LDO1 output voltage validity (raw status): 0 - LDO1 output voltage is valid. 1 - LDO1 output voltage is invalid. 5 Reserved - do not use R 0 4 LDO1_ILIM _STAT R 0 Status bit indicating the LDO1 current limit status (raw status): 0 - LDO1 output current is below the current limit level. 1 - LDO1 output current limit is active. 3 LDO0_STAT R 0 Status bit indicating the enable and disable status of the LDO0: 0 - LDO0 regulator is disabled. 1 - LDO0 regulator is enabled. 2 LDO0_PG_STAT R 0 Status bit indicating the LDO0 output voltage validity (raw status): 0 - LDO0 output voltage is valid. 1 - LDO0 output voltage is invalid. 1 Reserved - do not use R 0 0 LDO0_ILIM _STAT R 0 Status bit indicating the LDO0 current limit status (raw status): 0 - LDO0 output current is below the current limit level. 1 - LDO0 output current limit is active. 7.6.1.33 TOP_MASK_1 TOP_MASK_1 is shown in Table 7-73, Address: 0x20 Table 7-72. TOP_MASK_1 Register D7 D6 D5 D4 D3 D2 D1 D0 PGOOD_INT_ MASK Reserved - do not use SYNC_CLK _MASK Reserved - do not use TDIE_WARN _MASK Reserved - do not use I_LOAD_ READY_MASK Table 7-73. TOP_MASK_1 Register Field Descriptions Bits Field Type Default Description 7 PGOOD_INT _MASK R/W X Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register): 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the PGOOD_STAT status bit in the TOP_STAT register. 6:5 Reserved - do not use R/W 00 www.ti.com LP8733-Q1 SNVSB64A – JUNE 2019 – REVISED JUNE 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: LP8733-Q1 |
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