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LP8733-Q1 Datasheet(PDF) 47 Page - Texas Instruments |
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LP8733-Q1 Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 86 page  Table 7-27. LDO1_CTRL Register Field Descriptions (continued) Bits Field Type Default Description 2 LDO1_RDIS_EN R/W 1 Enable output discharge resistor (RDIS_LDOx) when the LDO1 is disabled: 0 - Discharge resistor is disabled. 1 - Discharge resistor is enabled. 1 LDO1_EN_PIN _CTRL R/W X Enable control for the LDO1: 0 - only the LDO1_EN bit controls the LDO1. 1 - LDO1_EN bit and the EN pin control the LDO1. 0 LDO1_EN R/W X Enable the LDO1 regulator: 0 - LDO1 regulator is disabled. 1 - LDO1 regulator is enabled. 7.6.1.11 LDO0_VOUT LDO0_VOUT is shown in Table 7-29, Address: 0x0A Table 7-28. LDO0_VOUT Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved - do not use LDO0_VSET[4:0] Table 7-29. LDO0_VOUT Register Field Descriptions Bits Field Type Default Description 7:5 Reserved - do not use R/W 000 4:0 LDO0_VSET[4:0] R/W X Sets the output voltage of the LDO0 regulator: 0.8 V - 3.3 V, 100 mV steps 0x00 - 0.8V ... 0x19 - 3.3 V Reserved; do not use. 0x1A ... 0x1F 7.6.1.12 LDO1_VOUT LDO1_VOUT is shown in Table 7-31, Address: 0x0B Table 7-30. LDO1_VOUT Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved - do not use LDO1_VSET[4:0] Table 7-31. LDO1_VOUT Register Field Descriptions Bits Field Type Default Description 7:5 Reserved - do not use R/W 000 4:0 LDO1_VSET[4:0] R/W X Sets the output voltage of the LDO1 regulator: 0.8 V - 3.3 V, 100 mV steps 0x00 - 0.8V ... 0x19 - 3.3 V Reserved; do not use. 0x1A ... 0x1F 7.6.1.13 BUCK0_DELAY BUCK0_DELAY is shown in Table 7-33, Address: 0x0C Table 7-32. BUCK0_DELAY Register D7 D6 D5 D4 D3 D2 D1 D0 www.ti.com LP8733-Q1 SNVSB64A – JUNE 2019 – REVISED JUNE 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LP8733-Q1 |
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