UPSD3313D-40T6 datasheet(49/231 Pages) STMICROELECTRONICS

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uPSD33xx

MCU firmware may reduce the MCU clock fre-

quency at run-time to consume less current when

performing tasks that are not time critical, and then

restore full clock frequency as required to perform

urgent tasks.

Returning to full clock frequency is done automat-

ically upon an MCU interrupt, if the CPUAR Bit in

the SFR named CCON0 is set (the interrupt will

force CPUPS[2:0] = 000). This is an excellent way

to conserve power using a low frequency clock un-

til an event occurs that requires full performance.

See Table 21., page 47 for details on CPUAR.

See the DC Specifications at the end of this docu-

ment to estimate current consumption based on

the MCU clock frequency.

Note: Some of the bits in the PCON SFR shown in

Table 24., page 50 are not related to power con-

trol.

Table 22. MCU Module Port and Peripheral Status during Reduced Power Modes

Note: 1. The Watchdog Timer is not active during Idle Mode. Other supervisor functions are active: LVD, external reset, JTAG Debug reset

Table 23. State of 8032 MCU Bus Signals during Power-down and Idle Modes

Mode

Ports 1, 3, 4

PCA

SPI

I2C

ADC

SUPER-

VISOR

UART0,

UART1

TIMER

0,1,2

EXT

INT0, 1

Idle

Maintain Data

Active

Active(1)

Active

Power-down

Maintain Data

Disabled

Mode

ALE

PSEN_

RD_

WR_

AD0-7

A8-15

Idle

011

FFh

Power-down

FFh

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