UPSD3313D-40T6 datasheet(37/231 Pages) STMICROELECTRONICS

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uPSD33xx

DUAL DATA POINTERS

XDATA is accessed by the External Direct ad-

dressing mode, which uses a 16-bit address

stored in the DPTR Register. Traditional 8032 ar-

chitecture has only one DPTR Register. This is a

burden when transferring data between two XDA-

TA locations because it requires heavy use of the

working registers to manipulate the source and

destination pointers.

However, the uPSD33xx has two data pointers,

one for storing a source address and the other for

storing a destination address. These pointers can

be configured to automatically increment or decre-

ment after each data transfer, further reducing the

burden on the 8032 and making this kind of data

movement very efficient.

Data Pointer Control Register, DPTC (85h)

By default, the DPTR Register of the uPSD33xx

will behave no different than in a standard 8032

MCU. The DPSEL0 Bit of SFR register DPTC

shown in Table 13, selects which one of the two

“background” data pointer registers (DPTR0 or

DPTR1) will function as the traditional DPTR Reg-

ister at any given time. After reset, the DPSEL0 Bit

is cleared, enabling DPTR0 to function as the DP-

TR, and firmware may access DPTR0 by reading

or writing the traditional DPTR Register at SFR ad-

dresses 82h and 83h. When the DPSEL0 bit is set,

then the DPTR1 Register functions as DPTR, and

firmware may now access DPTR1 through SFR

registers at 82h and 83h. The pointer which is not

selected by the DPSEL0 bit remains in the back-

ground and is not accessible by the 8032. If the

DPSEL0 bit is never set, then the uPSD33xx will

behave like a traditional 8032 having only one

DPTR Register.

To further speed XDATA to XDATA transfers, the

SFR bit, AT, may be set to automatically toggle the

two data pointers, DPTR0 and DPTR1, each time

the standard DPTR Register is accessed by a

MOVX instruction. This eliminates the need for

firmware to manually manipulate the DPSEL0 bit

between each data transfer.

Detailed description for the SFR register DPTC is

shown in Table 13.

Table 13. DPTC: Data Pointer Control Register (SFR 85h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

–––––

DPSEL0

Details

Bit

Symbol

R/W

Definition

7––

Reserved

6AT

R,W

0 = Manually Select Data Pointer

1 = Auto Toggle between DPTR0 and DPTR1

5-1

–

Reserved

DPSE0

R,W

0 = DPTR0 Selected for use as DPTR

1 = DPTR1 Selected for use as DPTR

UPSD3313D-40T6 Datasheet(PDF) 37 Page - STMicroelectronics

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