UPSD3313D-40T6 datasheet(97/231 Pages) STMICROELECTRONICS

No. de pieza	UPSD3313D-40T6

Descripción Electrónicos	Fast 8032 MCU with Programmable Logic

PDF	231 Pages

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Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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uPSD33xx

–

An Acknowlegde bit is generated from a

Master or a Slave by driving SDA low during

the “ninth” bit time, just following each 8-bit

byte that is transfered on the bus (Figure

39., page 97). A Non-Acknowledge occurs

when SDA is asserted high during the ninth bit

time. All byte transfers on the I2C bus include

a 9th bit time reserved for an Acknowlege

(ACK) or Non-Acknowledge (NACK).

–

An additional Master device that desires to

control the bus should wait until the bus is not

busy before generating a START condition so

that a possible Slave operation is not

interrupted.

–

If two Master devices both try to generate a

START condition simultaneously, the Master

who looses arbitration will switch immediately

to Slave mode so it can recoginize it’s own

Slave address should it appear on the bus.

Figure 39. Data Transfer on an I2C Bus

MSB

7-bit Slave

Address

READ/WRITE

Indicator

Acknowledge

bits from

receiver

Start

Condition

Clock can be held low

to stall transfer.

Repeated if more

data bytes are

transferred.

Repeated

Start

Condition

Stop

Condition

3-6

3-8

MSB

ACK

NACK

R/W

AI09625

UPSD3313D-40T6 Datasheet(PDF) 97 Page - STMicroelectronics

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