UPSD3313D-40T6 datasheet(46/231 Pages) STMICROELECTRONICS

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uPSD33xx

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MCU CLOCK GENERATION

Internal system clocks generated by the clock gen-

eration unit are derived from the signal, XTAL1,

shown in Figure 14. XTAL1 has a frequency fOSC,

which comes directly from the external crystal or

oscillator device. The SFR named CCON0 (Table

21., page 47) controls the clock generation unit.

There are two clock signals produced by the clock

generation unit:

■

MCU_CLK

■

PERIPH_CLK

MCU_CLK

This clock drives the 8032 MCU core and the

Watchdog

Timer

(WDT).

The

frequency

MCU_CLK is equal to fOSC by default, but it can be

divided by as much as 2048, shown in Figure 14.

The bits CPUPS[2:0] select one of eight different

divisors, ranging from 2 to 2048. The new frequen-

cy is available immediately after the CPUPS[2:0]

bits are written. The final frequency of MCU_CLK

is fMCU.

MCU_CLK is blocked by either bit, PD or IDL, in

the SFR named PCON during MCU Power-down

Mode or Idle Mode respectively.

MCU_CLK clock can be further divided as re-

quired for use in the WDT. See details of the WDT

in SUPERVISORY FUNCTIONS, page 65.

PERIPH_CLK

This clock drives all the uPSD33xx peripherals ex-

cept the WDT. The Frequency of PERIPH_CLK is

always fOSC. Each of the peripherals can indepen-

dently divide PERIPH_CLK to scale it appropriate-

ly for use.

PERIPH_CLK runs at all times except when

blocked by the PD bit in the SFR named PCON

during MCU Power-down Mode.

JTAG Interface Clock. The JTAG interface for

ISP and for Debugging uses the externally sup-

plied JTAG clock, coming in on pin TCK. This

means the JTAG ISP interface is always available,

and the JTAG Debug interface is available when

enabled, even during MCU Idle mode and Power-

down Mode.

However, since the MCU participates in the JTAG

debug process, and MCU_CLK is halted during

Idle and Power-down Modes, the majority of de-

bug functions are not available during these low

power modes. But the JTAG debug interface is ca-

pable of executing a reset command while in these

low power modes, which will exit back to normal

operating mode where all debug commands are

available again.

The CCON0 SFR contains a bit, DBGCE, which

enables the breakpoint comparators inside the

JTAG Debug Unit when set. DBGCE is set by de-

fault after reset, and firmware may clear this bit at

run-time. Disabling these comparators will reduce

current consumption on the MCU Module, and it’s

recommended to do so if the Debug Unit will not

be used (such as in the production version of an

end-product).

Figure 14. Clock Generation Logic

XTAL1 /2

XTAL1 /4

XTAL1 /2048

XTAL1 (default)

XTAL1 /8

XTAL1 /16

XTAL1 /32

XTAL1 /1024

XTAL1

(fOSC)

PCON[1]: PD,

Power-Down Mode

PCON[2:0]: CPUPS[2:0],

Clock Pre-Scaler Select

PCON[0]: IDL,

Idle Mode

Clock Divider

MCU_CLK (fMCU)

(to: 8032, WDT)

PERIPH_CLK (fOSC)

(to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC)

AI09197

UPSD3313D-40T6 Datasheet(PDF) 46 Page - STMicroelectronics

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