M38039G8HKP datasheet(17/92 Pages) RENESAS

17 / 92 page

Rev.1.10

Nov 14, 2005

Page 17 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

I/O PORTS

The I/O ports have direction registers which determine the

input/output direction of each individual pin. Each bit in a

direction register corresponds to one pin, and each pin can be set

to be input port or output port.

When “0” is written to the bit corresponding to a pin, that pin

becomes an input pin. When “1” is written to that bit, that pin

becomes an output pin.

If data is read from a pin which is set to output, the value of the

port output latch is read, not the value of the pin itself. Pins set to

input are floating. If a pin set to input is written to, only the port

output latch is written to and the pin remains floating.

By setting the port P0 pull-up control register (address 0FF016)

to the port P6 pull-up control register (address 0FF616) ports can

control pull-up with a program. However, the contents of these

registers do not affect ports programmed as the output ports.

NOTES:

1. Refer to the applicable sections how to use double-function ports as function I/O ports.

2. Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

Table 8

I/O port function

Name

Input/

Output

I/O Structure

Non-Port Function

Related SFRs

Ref.

No.

P00/AN8

−P07/AN15

Port P0 Input/output,

individual

bits

CMOS compatible

input level

CMOS 3-state

output

A/D converter input

AD/DA control register

(1)

P10/INT41

P11/INT01

Port P1

External interrupt input

Interrupt edge selection register

(2)

P12

−P17

(3)

P20/LED0

−P27/LED7 Port P2

P30/DA1

P31

/DA2

Port P3

D/A converter output

AD/DA control register

(4)

P32, P33

CMOS compatible

input level

N-channel

open-drain output

(5)

P34/RXD3

P35/TXD3

P36/SCLK3

P37/SRDY3

CMOS compatible

input level

CMOS 3-state

output

Serial I/O3 function I/O

Serial I/O3 control register

UART3 control register

(6)

(7)

(8)

(9)

P40/INT40

/XCOUT

P41/INT00

/XCIN

Port P4

External interrupt input

Sub-clock generating circuit

Interrupt edge selection register

CPU mode register

(10)

(11)

P42/INT1

P43/INT2

External interrupt input

Interrupt edge selection register

(2)

P44/RXD1

P45/TXD1

P46/SCLK1

Serial I/O1 function I/O

Serial I/O1 control register

UART1 control register

(6)

(7)

(8)

P47/SRDY1/CNTR2

Serial I/O1 function I/O

Timer Z function I/O

Serial I/O1 control register

Timer Z mode register

(12)

P50/SIN2

P51/SOUT2

P52/SCLK2

P53/SRDY2

Port P5

Serial I/O2 function I/O

Serial I/O2 control register

(13)

(14)

(15)

(16)

P54/CNTR0

P55/CNTR1

Timer X, Y function I/O

Timer XY mode register

(17)

P56/PWM

PWM output

PWM control register

(18)

P57/INT3

External interrupt input

Interrupt edge selection register

(2)

P60/AN0

−P67/AN7

Port P6

A/D converter input

AD/DA control register

(1)

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