M38039G8HKP datasheet(56/92 Pages) RENESAS

56 / 92 page

Rev.1.10

Nov 14, 2005

Page 56 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

PULSE WIDTH MODULATION (PWM)

The 3803 group (Spec.H QzROM version) has PWM functions

with an 8-bit resolution, based on a signal that is the clock input

XIN or that clock input divided by 2 or the clock input XCIN or

that clock input divided by 2 in low-speed mode.

• Data Setting

The PWM output pin also functions as port P56. Set the PWM

period by the PWM prescaler, and set the “H” term of output

pulse by the PWM register.

If the value in the PWM prescaler is n and the value in the PWM

PWM period = 255 × (n+1) / f(XIN)

= 31.875 × (n+1)

µs

(when f(XIN) = 8 MHz, count source selection bit = “0”)

Output pulse “H” term = PWM period × m / 255

= 0.125 × (n+1) × m

µs

(when f(XIN) = 8 MHz, count source selection bit = “0”)

• PWM Operation

When bit 0 (PWM enable bit) of the PWM control register is set

to “1”, operation starts by initializing the PWM output circuit,

and pulses are output starting at an “H”.

If the PWM register or PWM prescaler is updated during PWM

output, the pulses will change in the cycle after the one in which

the change was made.

Fig 45. Timing of PWM period

Fig 46. Block diagram of PWM function

31.875

× m × (n+1)

255

µs

T = [31.875

× (n+1)] µs

PWM output

m : Contents of PWM register

n : Contents of PWM prescaler

T : PWM period

(when f(XIN) = 8 MHz, count source selection bit = “0”)

Data bus

Count source

selection bit

“0”

“1”

PWM

prescaler pre-latch

PWM

prescaler latch

PWM

Transfer control circuit

PWM register

1/2

XIN

(XCIN at low-

speed mode)

Port P56 latch

PWM function enable bit

Port P56

PWM prescaler

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