M38039G8HKP datasheet(57/92 Pages) RENESAS

57 / 92 page

Rev.1.10

Nov 14, 2005

Page 57 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 47. Structure of PWM control register

Fig 48. PWM output timing when PWM register or PWM prescaler is changed

<Notes>

The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.

The length of this “L” level output is as follows:

(Count source selection bit = 0, where n is the value set in the prescaler)

(Count source selection bit = 1, where n is the value set in the prescaler)

PWM control register

(PWMCON: address 002B16)

PWM function enable bit

0 : PWM disabled

1 : PWM enabled

Count source selection bit

0: f(XIN) (f(XCIN) at low-speed mode)

1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)

Not used

(return “0” when read)

PWM output

PWM register

write signal

PWM prescaler

write signal

(Changes “H” term from “A” to “ B”.)

(Changes PWM period from “T” to “T2”.)

When the contents of the PWM register or PWM prescaler have changed,

the PWM output will change from the next period after the change.

×fXIN

()

----------------------- sec

fXIN

()

---------------- sec

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