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M38039G8HKP Datasheet(PDF) 48 Page - Renesas Technology Corp |
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M38039G8HKP Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 92 page ![]() Rev.1.10 Nov 14, 2005 Page 48 of 91 REJ03B0166-0110 3803 Group (Spec.H QzROM version) PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. • Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register (address 001F16). [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight bits which control various serial I/O2 functions. Fig 37. Structure of Serial I/O2 control register Fig 38. Block diagram of serial I/O2 Serial I/O2 control register (SIO2CON : address 001D16) b7 Internal synchronous clock selection bits b2 b1 b0 00 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 00 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 01 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 01 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 11 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 11 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2, SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) b0 f(XIN) Serial I/O counter 2 (3) Serial I/O2 register (8) Synchronization circuit “1” “0” “0” “1” “0” “1” “0” “1” 1/8 1/16 1/32 1/64 1/128 1/256 Data bus Serial I/O2 interrupt request Serial I/O2 port selection bit Serial I/O2 port selection bit Serial I/O2 synchronous clock selection bit SRDY2 output enable bit External clock Internal synchronous clock selection bits P52/SCLK2 P51/SOUT2 P50/SIN2 P52 latch P51 latch P53 latch P53/SRDY2 (f(XCIN) in low-speed mode) SRDY2 Address 001F16 |
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