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M38039G8HKP Datasheet(PDF) 79 Page - Renesas Technology Corp |
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M38039G8HKP Datasheet(HTML) 79 Page - Renesas Technology Corp |
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79 / 92 page ![]() Rev.1.10 Nov 14, 2005 Page 79 of 91 REJ03B0166-0110 3803 Group (Spec.H QzROM version) PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. NOTES: 1. When the P35/TXD3 P4-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. Table 21 Switching characteristics (2) (VCC = 2.0 to 5.5 V, VSS = 0V, Ta = −20 to 85 °C, unless otherwise noted) Symbol Parameter Test conditions Limits Unit Min. Typ. Max. tf(SCLK2) Serial I/O2 fall time of clock output 4.5 ≤ VCC ≤ 5.5 V Fig.64 30 ns 4.0 ≤ VCC < 4.5 V 35 2.7 ≤ VCC < 4.0 V 40 2.2 ≤ VCC < 2.7 V 45 2.0 ≤ VCC < 2.2 V 50 tr(CMOS) CMOS rise time of output(1) 4.5 ≤ VCC ≤ 5.5 V 10 30 ns 4.0 ≤ VCC < 4.5 V 12 35 2.7 ≤ VCC < 4.0 V 15 40 2.2 ≤ VCC < 2.7 V 17 45 2.0 ≤ VCC < 2.2 V 20 50 tf(CMOS) CMOS fall time of output(1) 4.5 ≤ VCC ≤ 5.5 V 10 30 ns 4.0 ≤ VCC < 4.5 V 12 35 2.7 ≤ VCC < 4.0 V 15 40 2.2 ≤ VCC < 2.7 V 17 45 2.0 ≤ VCC < 2.2 V 20 50 |
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