M38039G8HKP datasheet(71/92 Pages) RENESAS

71 / 92 page

Rev.1.10

Nov 14, 2005

Page 71 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Recommended operating conditions

NOTES:

1. When using A/D converter, see A/D converter recommended operating conditions.

2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating

temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation.

3. When the oscillation frequency has a duty cycle of 50%.

4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.

Table 11

Recommended operating conditions (1)

(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Symbol

Parameter

Conditions

Limits

Unit

Min.

Typ.

Max.

VCC

Power source

voltage(1)

When start oscillating(2)

2.2

5.0

5.5

High-speed mode

φ) = f(XIN)/2

f(XIN)

≤ 2.1 MHz

2.0

5.0

5.5

f(XIN)

≤ 4.2 MHz

2.2

5.0

5.5

f(XIN)

≤ 8.4 MHz

2.7

5.0

5.5

f(XIN)

≤ 12.5 MHz

4.0

5.0

5.5

f(XIN)

≤ 16.8 MHz

4.5

5.0

5.5

Middle-speed mode

φ) = f(XIN)/8

f(XIN)

≤ 6.3 MHz

1.8

5.0

5.5

f(XIN)

≤ 8.4 MHz

2.2

5.0

5.5

f(XIN)

≤ 12.5 MHz

2.7

5.0

5.5

f(XIN)

≤ 16.8 MHz

4.5

5.0

5.5

VSS

Power source voltage

VIH

“H” input voltage

P00-P07, P10-P17,

P20-P27, P30, P31,

P34-P37, P40-P47,

P50-P57, P60-P67

1.8

≤ VCC < 2.7 V

0.85 VCC

VCC

2.7

≤ VCC ≤ 5.5 V

0.8 VCC

VCC

VIH

“H” input voltage

P32, P33

1.8

≤ VCC < 2.7 V

0.85 VCC

5.5

2.7

≤ VCC ≤ 5.5 V

0.8 VCC

5.5

VIH

“H” input voltage

RESET, XIN, XCIN,

CNVSS

1.8

≤ VCC < 2.7 V

0.85 VCC

VCC

2.7

≤ VCC ≤ 5.5 V

0.8 VCC

VCC

VIL

“L” input voltage

P00-P07, P10-P17,

P20-P27, P30-P37,

P40-P47, P50-P57,

P60-P67

1.8

≤ VCC < 2.7 V

0.16 VCC

2.7

≤ VCC ≤ 5.5 V

0.2 VCC

VIL

“L” input voltage

RESET, CNVSS

1.8

≤ VCC < 2.7 V

0.16 VCC

2.7

≤ VCC ≤ 5.5 V

0.2 VCC

VIL

“L” input voltage

XIN, XCIN

1.8

≤ VCC ≤ 5.5 V

0.16 VCC

f(XIN)

Main clock input

oscillation

frequency(3)

High-speed mode

φ) = f(XIN)/2

2.0

≤ VCC < 2.2 V

MHz

2.2

≤ VCC < 2.7 V

MHz

2.7

≤ VCC < 4.0 V

MHz

4.0

≤ VCC < 4.5 V

MHz

4.5

≤ VCC ≤ 5.5 V

16.8

MHz

Middle-speed mode

φ) = f(XIN)/8

1.8

≤ VCC < 2.2 V

MHz

2.2

≤ VCC < 2.7 V

MHz

2.7

≤ VCC < 4.5 V

MHz

4.5

≤ VCC ≤ 5.5 V

16.8

MHz

f(XCIN)

Sub-clock input oscillation frequency(3, 4)

32.768

kHz

VCC

–

() 1.05

-----------------------------------------------------------

VCC

40.8

–

() 1.05

----------------------------------------------------------------

9VCC

0.3

–

() 1.05

----------------------------------------------------------

VCC

–

() 1.05

-----------------------------------------------------------

VCC

–

() 1.05

--------------------------------------------------------

VCC

28.8

–

() 1.05

----------------------------------------------------------------

VCC

() 1.1

--------------------------------------------------------

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