M38039G8HKP datasheet(6/92 Pages) RENESAS

6 / 92 page

Rev.1.10

Nov 14, 2005

Page 6 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

PIN DESCRIPTION

Table 4

Pin description

Name

Functions

Function except a port function

VCC, VSS

Power source

• Apply voltage of 1.8 V

− 5.5 V to VCC, and 0 V to VSS.

CNVSS

CNVSS input

• This pin controls the operation mode of the chip and is shared with the VPP pin which is the

power source input pin for programming the built-in QzROM.

• Normally connected to VSS.

VREF

Reference

voltage

• Reference voltage input pin for A/D and D/A converters.

AVSS

Analog power

source

• Analog power source input pin for A/D and D/A converters.

• Connect to VSS.

RESET

Reset input

• Reset input pin for active “L”.

XIN

Clock input

• Input and output pins for the clock generating circuit.

• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set

the oscillation frequency.

• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin

open.

XOUT

Clock output

P00/AN8

−

P07/AN15

I/O port P0

• 8-bit CMOS I/O port.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level.

• CMOS 3-state output structure.

• Pull-up control is enabled in a bit unit.

•P20

− P27 (8 bits) are enabled to output large current for

LED drive.

• A/D converter input pin

P10/INT41

P11/INT01

I/O port P1

• Interrupt input pin

P12

−P17

P20-P27

I/O port P2

P30/DA1

P31

/DA2

I/O port P3

• 8-bit CMOS I/O port.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level.

•P30, P31, P34

− P37 are CMOS 3-state output structure.

•P32, P33 are N-channel open-drain output structure.

• Pull-up control of P30, P31, P34

− P37 is enabled in a bit unit.

• D/A converter input pin

P32, P33

P34/RXD3

P35/TXD3

P36/SCLK3

P37/SRDY3

• Serial I/O3 function pin

P40/INT40

/XCOUT

P41/INT00

/XCIN

I/O port P4

• 8-bit CMOS I/O port.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level.

• CMOS 3-state output structure.

• Pull-up control is enabled in a bit unit.

• Interrupt input pin

• Sub-clock generating I/O pin

(resonator connected)

P42/INT1

P43/INT2

• Interrupt input pin

P44/RXD1

P45/TXD1

P46/SCLK1

• Serial I/O1 function pin

P47/SRDY1/CNTR2

• Serial I/O1, timer Z function pin

P50/SIN2

P51/SOUT2

P52/SCLK2

P53/SRDY2

I/O port P5

• Serial I/O2 function pin

P54/CNTR0

• Timer X function pin

P55/CNTR1

• Timer Y function pin

P56/PWM

• PWM output pin

P57/INT3

• Interrupt input pin

P60/AN0

−

P67/AN7

I/O port P6

• A/D converter input pin

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