M38039G8HKP datasheet(88/92 Pages) RENESAS

88 / 92 page

Rev.1.10

Nov 14, 2005

Page 88 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Notes on Serial Interface

1. Notes when selecting clock synchronous serial I/O

(1) Stop of transmission operation

As for serial I/Oi (i = 1, 3) that can be used as either a clock

synchronous or an asynchronous (UART) serial I/O, clear the

serial I/Oi enable bit and the transmit enable bit to “0” (serial

I/Oi and transmit disabled).

Since transmission is not stopped and the transmission circuit is

not initialized even if only the serial I/Oi enable bit is cleared to

“0” (serial I/Oi disabled), the internal transmission is running (in

this case, since pins TxDi, RxDi, SCLKi, and SRDYi function as

I/O ports, the transmission data is not output). When data is

written to the transmit buffer register in this state, data starts to

be shifted to the transmit shift register. When the serial I/Oi

enable bit is set to “1” at this time, the data during internally

shifting is output to the TxDi pin and an operation failure occurs.

(2) Stop of receive operation

As for serial I/Oi (i = 1, 3) that can be used as either a clock

synchronous or an asynchronous (UART) serial I/O, clear the

receive enable bit to “0” (receive disabled), or clear the serial

I/Oi enable bit to “0” (serial I/Oi disabled).

(3) Stop of transmit/receive operation

As for serial I/Oi (i = 1, 3) that can be used as either a clock

synchronous or an asynchronous (UART) serial I/O, clear both

the transmit enable bit and receive enable bit to “0” (transmit and

receive disabled).

(when data is transmitted and received in the clock synchronous

serial I/O mode, any one of data transmission and reception

cannot be stopped.)

In the clock synchronous serial I/O mode, the same clock is used

for transmission and reception. If any one of transmission and

reception is disabled, a bit error occurs because transmission and

reception cannot be synchronized.

In this mode, the clock circuit of the transmission circuit also

operates for data reception. Accordingly, the transmission circuit

does not stop by clearing only the transmit enable bit to “0”

(transmit disabled). Also, the transmission circuit is not

initialized by clearing the serial I/Oi enable bit to “0” (serial I/Oi

disabled) (refer to (1) in 1.).

2. Notes when selecting clock asynchronous serial I/O

(1) Stop of transmission operation

Clear the transmit enable bit to “0” (transmit disabled). The

transmission operation does not stop by clearing the serial I/Oi

enable bit (i = 1, 3) to “0”.

This is the same as (1) in 1.

(2) Stop of receive operation

Clear the receive enable bit to “0” (receive disabled).

(3) Stop of transmit/receive operation

Only transmission operation is stopped.

Clear the transmit enable bit to “0” (transmit disabled). The

transmission operation does not stop by clearing the serial I/Oi

enable bit (i = 1, 3) to “0”.

This is the same as (1) in 1.

Only receive operation is stopped.

Clear the receive enable bit to “0” (receive disabled).

3. SRDYi (i = 1, 3) output of reception side

When signals are output from the SRDYi pin on the reception side

by using an external clock in the clock synchronous serial I/O

mode, set all of the receive enable bit, the SRDYi output enable

bit, and the transmit enable bit to “1” (transmit enabled).

4. Setting serial I/Oi (i = 1, 3) control register again

Set the serial I/Oi control register again after the transmission

and the reception circuits are reset by clearing both the transmit

enable bit and the receive enable bit to “0.”

Fig 6.

Sequence of setting serial I/Oi (i = 1, 3) control

5. Data transmission control with referring to transmit

shift register completion flag

After the transmit data is written to the transmit buffer register,

the transmit shift register completion flag changes from “1” to

“0” with a delay of 0.5 to 1.5 shift clocks. When data

transmission is controlled with referring to the flag after writing

the data to the transmit buffer register, note the delay.

6. Transmission control when external clock is selected

When an external clock is used as the synchronous clock for data

transmission, set the transmit enable bit to “1” at “H” of the

SCLKi (i = 1, 3) input level. Also, write the transmit data to the

transmit buffer register at “H” of the SCLKi input level.

7. Transmit interrupt request when transmit enable bit

is set

When using the transmit interrupt, take the following sequence.

(1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to

“0” (disabled).

(2) Set the tranasmit enable bit to “1”.

(3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to

“0” after 1 or more instruction has executed.

(4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to

“1” (enabled).

When the transmission enable bit is set to “1”, the transmit buffer

empty flag and transmit shift register shift completion flag are

also set to “1”.

Therefore, regardless of selecting which timing for the

generating of transmit interrupts, the interrupt request is

generated and the transmit interrupt request bit is set at this point.

8. Writing to baud rate generator i (BRGi) (i = 1, 3)

Write data to the baud rate generator i (BRGi) (i = 1, 3) while the

transmission/reception operation is stopped.

Can be set with the

LDM instruction at

the same time

Set the bits 0 to 3 and bit 6 of the serial I/Oi

control register

Clear both the transmit enable bit (TE) and

the receive enable bit (RE) to “0”

Set both the transmit enable bit (TE) and the

receive enable bit (RE), or one of them to “1”

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