M38039G8HKP datasheet(61/92 Pages) RENESAS

61 / 92 page

Rev.1.10

Nov 14, 2005

Page 61 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example,

because of a software run-away). The watchdog timer consists of

an 8-bit watchdog timer L and an 8-bit watchdog timer H.

• Watchdog Timer Initial Value

Watchdog timer L is set to “FF16” and watchdog timer H is set to

“FF16” by writing to the watchdog timer control register (address

001E16) or at a reset. Any write instruction that causes a write

signal can be used, such as the STA, LDM, CLB, etc. Data can

only be written to bits 6 and 7 of the watchdog timer control

mentioned value will be set to each timer.

• Watchdog Timer Operations

The watchdog timer stops at reset and starts to count down by

writing to the watchdog timer control register (address 001E16).

An internal reset occurs at an underflow of the watchdog timer

H. The reset is released after waiting for a reset release time and

the program is processed from the reset vector address.

Accordingly, programming is usually performed so that writing

to the watchdog timer control register may be started before an

underflow. If writing to the watchdog timer control register is not

performed once, the watchdog timer does not function.

• Bit 6 of Watchdog Timer Control Register

• When bit 6 of the watchdog timer control register is “0”, the

MCU enters the stop mode by execution of STP instruction.

Just after releasing the stop mode, the watchdog timer restarts

counting(Note.). When executing the WIT instruction, the

watchdog timer does not stop.

• When bit 6 is “1”, execution of STP instruction causes an

internal reset. When this bit is set to “1” once, it cannot be

rewritten to “0” by program. Bit 6 is “0” at reset.

The following shows the period between the write execution to

the watchdog timer control register and the underflow of

watchdog timer H.

Bit 7 of the watchdog timer control register is “0”:

when XCIN = 32.768 kHz; 32 s

when XIN = 16 MHz; 65.536 ms

Bit 7 of the watchdog timer control register is “1”:

when XCIN = 32.768 kHz; 125 ms

when XIN = 16 MHz; 256

µs

Note. The watchdog timer continues to count even while waiting for a

stop release. Therefore, make sure that watchdog timer H does not

underflow during this period.

Fig 54. Block diagram of Watchdog timer

Fig 55. Structure of Watchdog timer control register

XIN

Data bus

XCIN

“10”

“00”

“01”

Main clock division

ratio selection bits (Note)

“0”

“1”

1/16

Watchdog timer H count

source selection bit

Reset

circuit

STP instruction function selection bit

Watchdog timer H (8)

“FF16” is set when

watchdog timer

control register is

written to.

Internal reset

Watchdog timer L (8)

“FF16” is set when

watchdog timer

control register is

written to.

Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

STP instruction

RESET

Watchdog timer H (for read-out of high-order 6 bit)

STP instruction function selection bit

0: Entering stop mode by execution of STP instruction

1: Internal reset by execution of STP instruction

Watchdog timer H count source selection bit

0: Watchdog timer L underflow

1: f(XIN)/16 or f(XCIN)/16

Watchdog timer control register

(WDTCON : address 001E16)

M38039G8HKP Datasheet(PDF) 61 Page - Renesas Technology Corp

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