LP8733 datasheet(53/86 Pages) TI2

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Table 7-54. PG_FAULT Register

Reserved - do not use

PG_FAULT_LD

PG_FAULT_BU

CK1

PG_FAULT_BU

CK0

Table 7-55. PG_FAULT Register Field Descriptions

Bits

Field

Type

Default

Description

7:4

Reserved - do not

use

R/W

0000

PG_FAULT_LDO1

R/W

Source for the PGOOD inactive signal:

0 - LDO1 has not set the PGOOD signal inactive.

1 - LDO1 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the LDO1 output is valid.

PG_FAULT_LDO0

R/W

Source for PGOOD inactive signal:

0 - LDO0 has not set the PGOOD signal inactive.

1 - LDO0 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the LDO0 output is valid.

PG_FAULT_BUCK1

R/W

Source for PGOOD inactive signal:

0 - Buck1 has not set PGOOD signal inactive.

1 - Buck1 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the Buck1 output is valid.

PG_FAULT_BUCK0

R/W

Source for PGOOD inactive signal:

0 - Buck0 has not set PGOOD signal inactive.

1 - Buck0 is selected for the PGOOD signal and it has set the PGOOD signal inactive.

This bit can be cleared by writing '1' to this bit when the Buck0 output is valid.

7.6.1.25 RESET

RESET is shown in Table 7-57, Address: 0x18

Table 7-56. RESET Register

Reserved - do not use

SW_RESET

Table 7-57. RESET Register Field Descriptions

Bits

Field

Type

Default

Description

7:1

Reserved - do not

use

R/W

000 0000

SW_RESET

R/W

Software commanded reset. When written to 1, the registers will be reset to the

default values, the OTP memory is read, and the I2C interface is reset.

The bit is automatically cleared.

7.6.1.26 INT_TOP_1

INT_TOP_1 is shown in Table 7-59, Address: 0x19

Table 7-58. INT_TOP_1 Register

PGOOD_INT

LDO_INT

BUCK_INT

SYNC_CLK_IN

TDIE_SD_INT

TDIE_WARN_I

OVP_INT

I_MEAS_INT

Table 7-59. INT_TOP_1 Register Field Descriptions

Bits

Field

Type

Default

Description

PGOOD_INT

R/W

Latched status bit indicating that the PGOOD pin has changed from active to inactive.

Write 1 to clear interrupt.

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LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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