LP8733 datasheet(36/86 Pages) TI2

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7.3.8.4 Fault (Power Down)

7.3.8.4.1 Undervoltage Lockout

When the input voltage falls below the VANAUVLO at the VANA pin, the buck and LDO regulators are disabled

immediately (without switching ramp and shutdown delays), the output capacitor is discharged using the

pulldown resistor, and the LP8733xx-Q1 device enters SHUTDOWN. When the V(VANA) voltage is above the

VANAUVLO threshold level, the device powers up to STANDBY state.

If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register),

then the RESET_REG_INT interrupt bit in the INT_TOP_2 register indicates that the device has been in

SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host

processor reads the RESET_REG_INT interrupt bit after detecting an nINT low signal, then it detects that the

input supply voltage has been below the VANAUVLO level (or the host has requested reset with the SW_RESET

bit in the RESET register), and the registers are reset to default values.

7.3.9 Operation of the GPO Signals

The LP8733xx-Q1 device supports up to two general purpose output signals, GPO and GPO2. The GPO2 signal

is multiplexed with the CLKIN signal. The selection between the CLKIN and GPO2 pin function is set with the

CLKIN_PIN_SEL bit in the CONFIG register.

The GPO pins are configured with the following bits:

• The GPOx_OD bit in The GPO_CTRL register defines the type of the output, either push-pull with V(VANA)

level or open drain.

The logic level of the GPOx pin is set by the EN_GPOx bit in the GPO_CTRL register.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence

with an EN pin is selected by the GPOx_EN_PIN_CTRL bit in the GPO_CTRL register. For start-up and

shutdown sequence control, see Section 7.3.6.

7.3.10 Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.

This results as an accuracy of one clock period for the debounce window.

Table 7-5. Digital Signal Filtering

EVENT

SIGNAL/SUPPLY

RISING EDGE

FALLING EDGE

LENGTH

Enable/disable for BUCKx,

LDOx or GPOx

3 µs(1)

VANA UVLO

VANA

3 µs(1) (VANA voltage rising)

Immediate (VANA voltage falling)

VANA overvoltage

VANA

1 µs (VANA voltage rising)

20 µs (VANA voltage falling)

Thermal warning

TDIE_WARN_INT

20 µs

Thermal shutdown

TDIE_SD_INT

20 µs

Current limit

VOUTx_ILIM

20 µs

Overload

FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

1 ms

N/V

PGOOD pin and power-good

interrupt

PGOOD / FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

6 µs

(1)

No glitch filtering, only synchronization.

LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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