LP8733 datasheet(22/86 Pages) TI2

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24 MHz

Oscillator

CLKIN

Divider

´(;7

_CLK

_)5(4´

PLL

Divider

CLKIN

Detector

Clock Select

Logic

Internal

24 MHz

clock

1 MHz

´(1

_3//´

24 MHz

Figure 7-5. Clock and PLL Module

Table 7-2. PLL Operation

DEVICE

OPERATION MODE

EN_PLL

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

CLOCK

STANDBY

Disabled

Internal RC

ACTIVE

Disabled

Internal RC

STANDBY

Enabled

When external clock

appears or disappears

Automatic change to external

clock when available

ACTIVE

Enabled

When external clock

appears or disappears

Automatic change to external

clock when available

7.3.3 Low-Dropout Linear Regulators (LDOs)

The LP8733xx-Q1 device includes two identical linear regulators, LDO0 and LDO1, which target analog loads

with low noise requirements. The LDO regulators deliver 0.8-V to 3.3-V regulated voltage rails from a 2.5-V to

5.5-V input voltage. Both regulators have dedicated inputs which can be higher or lower than the device system

voltage V(VANA) to minimize the power dissipation.

7.3.4 Power-Up

The power-up sequence for the LP8733xx-Q1 is as follows:

• The VANA and VIN_Bx reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on-

reset (POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms

before writing or reading data to the LP8733xx-Q1.

• The device enters standby mode.

• The host can change the default register setting by I2C if needed.

• The regulators can be enabled and disabled.

• The GPO signals can be controlled by the EN pin and the I2C interface.

Transitions between the operating modes are shown in Section 7.4.1.

LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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