LP8733 datasheet(51/86 Pages) TI2

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Table 7-47. CONFIG Register Field Descriptions (continued)

Bits

Field

Type

Default

Description

SHUTDOWN_DELA

Y_SEL

R/W

Shutdown delay range from the EN signals:

0 - 0 ms - 7.5 ms with 0.5 ms steps

1 - 0 ms - 15 ms with 1 ms steps

CLKIN_PIN_SEL

R/W

CLKIN pin function:

0 - GPO2

1 - CLKIN

CLKIN_PD

R/W

Selects the pull down resistor on the CLKIN input pin (valid also when selected as

GPO2):

0 - Pull-down resistor is disabled.

1 - Pull-down resistor is enabled.

EN_PD

R/W

Selects the pull down resistor on the EN input pin.

0 - Pull-down resistor is disabled.

1 - Pull-down resistor is enabled.

TDIE_WARN_

LEVEL

R/W

Thermal warning threshold level:

0 - 125°C

1 - 137°C

EN_SPREAD

_SPEC

R/W

Enable spread spectrum feature:

0 - Disabled

1 - Enabled

7.6.1.21 PLL_CTRL

PLL_CTRL is shown in Table 7-49, Address: 0x14

Table 7-48. PLL_CTRL Register

Reserved - do

not use

EN_PLL

Reserved - do

not use

EXT_CLK_FREQ[4:0]

Table 7-49. PLL_CTRL Register Field Descriptions

Bits

Field

Type

Default

Description

Reserved - do not

use

R/W

EN_PLL

R/W

Selection of the external clock and PLL operation:

0 - Forced to the internal RC oscillator. The PLL is disabled.

1 - PLL is enabled in the STANDBY and ACTIVE modes. Automatic external clock

use when available, and interrupt is generated if the external clock appears or

disappears.

Reserved - do not

use

R/W

This bit must be set to '''0 .''

4:0

EXT_CLK_FREQ[4:

R/W

Frequency of the external clock (CLKIN):

0x00 - 1 MHz

0x01 - 2 MHz

0x02 - 3 MHz

...

0x16 - 23 MHz

0x17 - 24 MHz

0x18...0x1F - Reserved - do not use

See electrical specification for the input clock frequency tolerance.

7.6.1.22 PGOOD_CTRL_1

PGOOD_CTRL_1 is shown in Table 7-51, Address: 0x15

Table 7-50. PGOOD_CTRL_1 Register

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LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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