LP8733 datasheet(29/86 Pages) TI2

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Table 7-4. Summary of Interrupt Signals

EVENT

DEVICE RESPONSE

INTERRUPT BIT

INTERRUPT MASK BIT

STATUS BIT

RECOVERY AND INTERRUPT

CLEAR

Buck current limit triggered

No effect

BUCK_INT

BUCKx_ILIM_INT

BUCKx_ILIM_MASK

BUCKx_ILIM_STAT

Write 1 to the BUCKx_ILIM_INT

bit.

Interrupt is not cleared if the

current limit is active

LDO current limit triggered

No effect

LDO_INT

LDOx_ILIM_INT

LDOx_ILIM_MASK

LDOx_ILIM_STAT

Write 1 to the LDOx_ILIM_INT bit

Interrupt is not cleared if the

current limit is active

Buck short circuit (VVOUT <

0.35 V at 1 ms after enable)

or overload (VVOUT decreasing

below 0.35 V during operation,

1-ms debounce)

Regulator disable

BUCK_INT

BUCKx_SC_INT

N/A

Write 1 to the BUCKx_SC_INT bit

LDO short circuit (VVOUT <

0.3 V at 1 ms after enable)

or overload (VVOUT decreasing

below 0.3 V during operation,

1-ms debounce)

Regulator disable

LDO_INT

LDOx_SC_INT

N/A

Write 1 to the LDOx_SC_INT bit

Thermal warning

No effect

TDIE_WARN_INT

TDIE_WARN_MASK

TDIE_WARN_STAT

Write 1 to tge TDIE_WARN_INT

bit

Interrupt is not cleared if the

temperature is above the thermal

warning level

Thermal shutdown

All the regulators are

disabled immediately, and

the GPO and GPO2 are

set to low

TDIE_SD_INT

N/A

TDIE_SD_STAT

Write 1 to the TDIE_SD_INT bit

Interrupt is not cleared if the

temperature is above the thermal

shutdown level

VANA overvoltage (VANAOVP)

All the regulators are

disabled immediately, and

the GPO and GPO2 are

set to low

OVP_INT

N/A

OVP_STAT

Write 1 to the OVP_INT bit

Interrupt is not cleared if the VANA

voltage is above the VANAOVP

level

Buck power good, output

voltage becomes valid

No effect

BUCK_INT

BUCKx_PG_INT

BUCKx_PGR_MASK

BUCKx_PG_STAT

Write 1 to the BUCKx_PG_INT bit

Buck power good, output

voltage becomes invalid

No effect

BUCK_INT

BUCKx_PG_INT

BUCKx_PGF_MASK

BUCKx_PG_STAT

Write 1 to the BUCKx_PG_INT bit

LDO Power good, output

voltage becomes valid

No effect

LDO_INT

LDOx_PG_INT

LDOx_PGR_MASK

LDOx_PG_STAT

Write 1 to the LDOx_PG_INT bit

LDO power good, output

voltage becomes invalid

No effect

LDO_INT

LDOx_PG_INT

LDOx_PGF_MASK

LDOx_PG_STAT

Write 1 to the LDOx_PG_INT bit

PGOOD pin changing from

active to inactive state(1)

No effect

PGOOD_INT

PGOOD_MASK

PGOOD_STAT

Write 1 to the PGOOD_INT bit

External clock appears or

disappears

No effect to regulators

SYNC_CLK_INT(2)

SYNC_CLK_MASK

SYNC_CLK_STAT

Write 1 to the SYNC_CLK_INT bit

Load current measurement is

ready

No effect

I_MEAS_INT

I_MEAS_MASK

N/A

Write 1 to the I_MEAS_INT bit

Supply voltage VANAUVLO

triggered (VANA falling)

Immediate shutdown and

the registers reset to

default values

N/A

Supply voltage VANAUVLO

triggered (VANA rising)

Startup and the registers

reset to default values

and the OTP bits are

loaded

RESET_REG_INT

RESET_REG_MASK

N/A

Write 1 to the RESET_REG_INT

bit

Software requested reset

Immediate shutdown is

followed by power up and

the registers are reset to

their default values

RESET_REG_INT

RESET_REG_MASK

N/A

Write 1 to the RESET_REG_INT

bit

(1)

The PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. The PGOOD_POL bit in the PGOOD_CTRL_1 register affects

only the PGOOD pin polarity, not the Power Good and PGOOD_INT interrupt polarity.

(2)

If the clock is not available when the clock detector is enabled, then an interrupt is generated during the clock-dector operation.

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LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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