LP8733 datasheet(35/86 Pages) TI2

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7.3.8.3.1 Short-Circuit and Overload Protection

A short-circuit protection feature allows the LP8733xx-Q1 to protect itself and the external components against

a short circuit at the output or against overload during start-up. For the buck and LDO regulators, the fault

thresholds are about 350 mV (buck) and 300 mV (LDO). The protection is triggered and the regulator is disabled

if the output voltage is below the threshold level (1 ms) after the regulator is enabled.

In a similar way, the overload situation is protected during normal operation. If the output voltage falls below 0.35

V and 0.3 V and remains below the threshold level for 1 ms, then the regulator is disabled.

In Buck regulator short-circuit and overload situations, the BUCKx_SC_INT bit in the INT_BUCK register and the

INT_BUCKx bit in the INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to

0, and the nINT signal is pulled low. In LDO regulator short-circuit and overload situations, the LDOx_SC_INT

bit in the INT_LDO register and the INT_LDOx bit in the INT_TOP_1 register are set to 1, the LDOx_STAT bit in

the LDO_STAT register is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by

writing 1 to the BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt, the regulator makes a

new start-up attempt if the regulator is in an enabled state.

7.3.8.3.2 Overvoltage Protection

The LP8733xx-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes.

If the input voltage rises above the VANAOVP voltage level, the following occurs:

• All regulators are disabled immediately (without switching ramp or shutdown delays).

• The pull-down resistors discharge the output voltages, if the pull-down resistors are enabled (the

BUCKx_RDIS_EN = 1 in the BUCKx_CTRL_1 register and the LDOx_RDIS_EN = 1 in the LDOx_CTRL

• The GPOs are set to logic low level.

• The nINT signal is pulled low.

• The OVP_INT bit in the INT_TOP_1 register is set to 1.

• The BUCKx_STAT bit in the BUCK_STAT register and the LDOx_STAT bit in the LDO_STAT register are set

to 0.

The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above the

overvoltage detection level, then the interrupt is not cleared. The host can read the status of the overvoltage

from the OVP_STAT bit in the TOP_STAT register. The regulators cannot be enabled as long as the input

voltage is above the overvoltage detection level or while the overvoltage interrupt is pending.

7.3.8.3.3 Thermal Shutdown

The LP8733xx-Q1 has an overtemperature protection function that operates to protect itself from short-term

misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are

disabled immediately (without switching ramp and shutdown delays), the TDIE_SD_INT bit in the INT_TOP_1

1 to the TDIE_SD_INT bit. If the temperature is above thermal shutdown level, then the interrupt is not cleared.

The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit in the TOP_STAT register.

The regulators cannot be enabled as long as the junction temperature is above the thermal shutdown level or

while the thermal shutdown interrupt is pending.

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LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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