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LP8733 Datasheet(PDF) 43 Page - Texas Instruments |
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LP8733 Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 86 page  7.6.1.1 DEV_REV DEV_REV is shown in Table 7-9, Address: 0x00 Table 7-8. DEV_REV Register D7 D6 D5 D4 D3 D2 D1 D0 DEVICE_ID[1:0] Reserved - do not use Table 7-9. DEV_REV Register Field Descriptions Bits Field Type Default Description 7:6 DEVICE_ID[1:0] R X Device specific ID code. 5:0 Reserved - do not use R 00 0010 7.6.1.2 OTP_REV OTP_REV is shown in Table 7-11, Address: 0x01 Table 7-10. OTP_REV Register D7 D6 D5 D4 D3 D2 D1 D0 OTP_ID[7:0] Table 7-11. OTP_REV Register Field Descriptions Bits Field Type Default Description 7:0 OTP_ID[7:0] R X Identification Code of the OTP EPROM Version. 7.6.1.3 BUCK0_CTRL_1 BUCK0_CTRL_1 is shown in Table 7-13, Address: 0x02 Table 7-12. BUCK0_CTRL_1 Register D7 D6 D5 D4 D3 D2 D1 D0 Reserved - do not use BUCK0_FPWM _MP BUCK0_FPWM BUCK0_RDIS_ EN BUCK0_EN_PI N_CTRL BUCK0_EN Table 7-13. BUCK0_CTRL_1 Register Field Descriptions Bits Field Type Default Description 7:5 Reserved - do not use R/W 000 4 BUCK0_FPWM _MP R/W X Forces the Buck0 regulator to always operate in the multi-phase and forced PWM operation mode: 0 - Automatic phase adding and shedding. 1 - Forced to multi-phase operation, 2 phases in the 2-phase configuration. 3 BUCK0_FPWM R/W X Buck0 mode selection: 0 - Automatic transitions between the PFM and PWM modes (AUTO mode). 1 - Forced to the PWM operation. 2 BUCK0_RDIS_EN R/W 1 Enable output discharge resistor (RDIS_Bx) when the Buck0 is disabled: 0 - Discharge resistor disabled. 1 - Discharge resistor enabled. 1 BUCK0_EN_PIN _CTRL R/W X Enable control for the Buck0: 0 - only the BUCK0_EN bit controls the Buck0. 1 - BUCK0_EN bit and the EN pin control the Buck0. 0 BUCK0_EN R/W X Enable the Buck0 regulator: 0 - Buck0 regulator is disabled. 1 - Buck0 regulator is enabled. www.ti.com LP8733-Q1 SNVSB64A – JUNE 2019 – REVISED JUNE 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LP8733-Q1 |
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