LP8733 datasheet(34/86 Pages) TI2

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Time

Voltage

VOUTx

300 mV

Time

Current

ILIMx

INT_LDO(LDOx_ILIM_INT)

20 µs

nINT

LDO_STAT(LDOx_STAT)

Resistive

pull-down

Regulator disabled by

digital

Host clearing the interrupt by writing to flags

New startup if

enable is valid

1 ms

INT_LDO(LDOx_SC_INT)

Figure 7-14. LDO Regulator Overload Situation

7.3.8.2.2 Thermal Warning

The LP8733xx-Q1 device includes a protection feature against overtemperature by setting an interrupt for the

host processor. The threshold level of the thermal warning is selected with the TDIE_WARN_LEVEL bit in the

CONFIG register.

If the LP8733xx-Q1 device temperature increases above the thermal warning level, then the device sets the

TDIE_WARN_INT bit in the INT_TOP_1 register and pulls the nINT pin low. The status of the thermal warning

can be read from the TDIE_WARN_STAT bit in the TOP_STAT register, and the interrupt is cleared by writing 1

to the TDIE_WARN_INT bit. The thermal warning interrupt can be masked by setting the TDIE_WARN_MASK

bit in the TOP_MASK_1 register to 1.

7.3.8.3 Protection (Regulator Disable)

If the regulator is disabled, because of protection or fault (short-circuit protection, overload protection, thermal

shutdown, input overvoltage protection, or UVLO), then the output power FETs are set to high-impedance mode

and the output pulldown resistor is enabled (if enabled with the BUCKx_RDIS_EN bit in the BUCKx_CTRL_1

defined by the output capacitance, load current, and resistance of the integrated pull-down resistor. The pull-

down resistors are active as long as the VANA voltage is above approximately a 1.2-V level.

LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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LP8733 Datasheet(PDF) 34 Page - Texas Instruments