M58PR256J datasheet(50/114 Pages) STMICROELECTRONICS

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Configuration Register

M58PR256J, M58PR512J

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Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will

perform. Refer to Section 10: Read modes for details on read operations.

The Configuration Register is set through the Command Interface using the Set

Configuration Register command. The Configuration Register is volatile: after a reset or a

power-down/power-up sequence, the register is set for Asynchronous Read (CR15=1) and

all bits return to their default value. The Configuration Register bits are described in Table 15

They specify the selection of the burst length, burst X latency and the read operation. Refer

to Figure 6 and Figure 7 for examples of synchronous burst configurations.

7.1

Read Select bit (CR15)

The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous

Read operations. When:

●

CR15 = 0:

–

read operations in the Main Array are performed in Synchronous Burst mode;

–

operations to read the Status Register, Electronic Signature, CFI and EFA are

performed in Single Synchronous mode (See Section 10.3: Single Synchronous

Read mode for details).

●

CR15 = 1:

–

read operations in the Main Array are performed in Asynchronous Page mode,

–

operations to read the Status Register, Electronic Signature, CFI and EFA are

performed in Asynchronous Random Access mode.

Synchronous Burst Read can be performed across banks.

On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.

7.2

X-Latency bits (CR14-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of

clock cycles between the address being latched and the first data becoming available.

For correct operation the X-Latency bits can only assume the values in Table 15:

Configuration Register.

Table 14 shows how to set the X-Latency parameter, taking into account the frequency used

to read the Flash memory in Synchronous mode.

Refer to Figure 6: X-latency and data output configuration example, for an example

waveform.

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