M58PR256J datasheet(59/114 Pages) STMICROELECTRONICS

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M58PR256J, M58PR512J

Read modes

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10.2

Synchronous Burst Read mode

In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It

is possible to perform burst reads across bank boundaries.

Synchronous Burst Read mode can only be used to read the memory array. For other read

operations, such as Read Status Register, Read CFI, Read Electronic Signature and Read

EFA, Single Synchronous Read or Asynchronous Random Access Read must be used.

In Synchronous Burst Read mode, the flow of the data output depends on parameters that

are configured in the Configuration Register.

A burst sequence starts at the first clock edge after the falling edge of Latch Enable or Chip

Enable, whichever occurs last. Addresses are internally incremented and data is output on

each data cycle after a delay which depends on the X latency bits CR14-CR11 of the

Configuration Register.

The number of Words to be output during a Synchronous Burst Read operation can be

configured as 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0).

The WAIT signal may be asserted to indicate to the system that an output delay will occur.

This delay will depend on the starting address of the burst sequence and on the burst

configuration.

WAIT is asserted during the X latency, the WAIT state and at the end of a 8 and 16 Word

burst. It is only de-asserted when output data are valid.

In Continuous Burst Read mode, a WAIT state will occur when crossing the first 16 Word

boundary if the start address is not 16 Word aligned.

The WAIT signal can be configured to be active Low or active High by setting CR10 in the

Configuration Register.

See Table 29: Synchronous Read ac characteristics, and Figure 12: Synchronous Burst

Read ac waveforms, for details.

10.3

Single Synchronous Read mode

Single Synchronous Read operations are similar to Synchronous Burst Read operations

except that the memory outputs the same data until the burst length requirements are

satisfied (according to Configuration Register bits CR2-CR0).

Single Synchronous Read operations are used to read the EFA, Electronic Signature, Status

When the addressed bank is in Read CFI, Read Status Register or Read Electronic

Signature mode, the WAIT signal is asserted during the X latency, the WAIT state and at the

end of a 4, 8 and 16 Word burst. It is only de-asserted when output data are valid.

See Table 29: Synchronous Read ac characteristics, and Figure 12: Synchronous Burst

Read ac waveforms, for details.

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