M58PR256J datasheet(95/114 Pages) STMICROELECTRONICS

95 / 114 page

M58PR256J, M58PR512J

Common Flash Interface

95/114

Table 49.

Extended Flash array bank and erase block region 1 information

Offset(1)

Data

Description

(P+3A)h = 144h

16h

Data size of this Bank Region Information Section (addressable locations

including this one)

(P+3B)h = 145h

00h

(P+3C)h = 146h

01h

Number of identical banks within Bank Region 1

(P+3D)h = 147h

00h

(P+3E)h = 148h

11h

Number of program or erase operations allowed in Bank Region 1:

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+3F)h = 149h

00h

Number of program or erase operations allowed in other banks while a

bank in this region is being erased

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+40)h = 14Ah

00h

Number of program or erase operations allowed in other banks while a

bank in this region is being erased

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+41)h = 14Bh

01h

Types of erase block regions in Bank Region 1

n = number of erase block regions with contiguous same-size erase

blocks.

Symmetrically blocked banks have one blocking region(2).

(P+42)h = 14Ch

03h

"Bank Region 1 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks in each bank

Bits 16-31: n×256 = number of bytes in erase block region

(P+43)h = 14Dh

00h

(P+44)h = 14Eh

20h

(P+45)h = 14Fh

00h

(P+46)h = 150h

64h

Bank Region 1 (Erase Block Type 1)

Minimum block erase cycles × 1000

(P+47)h = 151h

00h

(P+48)h = 152h

01h

Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used

BIts 5-7: reserved

(P+49)h = 153h

03h

Bank Region 1 (Erase Block Type 1): Page mode and Synchronous

mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

M58PR256J Datasheet(PDF) 95 Page - STMicroelectronics

M58PR256J Datasheet(HTML) 95 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL