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M58PR256J Datasheet(PDF) 45 Page - STMicroelectronics |
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M58PR256J Datasheet(HTML) 45 Page - STMicroelectronics |
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45 / 114 page ![]() M58PR256J, M58PR512J Status Register 45/114 6 Status Register The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during program and erase operations, if no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR9, SR8, SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 13: Status Register bits. Refer to Table 13 in conjunction with the following text descriptions. 6.1 Control Program Mode status bit (SR9) The Control Program Mode Status Bit, SR9, is used to indicate whether an error occurred when writing to a Program Region configured in the Control Program mode. The SR9 bit should be read once the Program/Erase Controller Status bit SR7 is set to ‘1’ (Program/Erase Controller inactive). SR9 is set to 1 when the user attempts to program Object data in a Control Mode region. When: ● SR9 = 0, the program operation has completed successfully, ● SR9 = 1, the program operation failed. Once set to ‘1’, SR9 can only be cleared by issuing a Clear Status Register command or through a hardware reset. SR9 should be cleared before a new program command is issued, otherwise the new command will appear to fail. |
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