M58PR256J datasheet(18/114 Pages) STMICROELECTRONICS

18 / 114 page

Bus operations

M58PR256J, M58PR512J

18/114

3.5

Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current

consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power

consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,

independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH

during a program or erase operation, the device enters Standby mode when finished.

3.6

Reset

During Reset mode the memory is deselected and the outputs are high impedance. The

memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the

Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If

Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory

content is no longer valid.

3.7

Deep Power-Down (DPD)

The memory enters the Deep Power-Down mode from the Standby mode (RP and E are de-

asserted, VIH) by setting ECR15 High (set to ‘1’) and asserting the DPD pin, whatever the

order of the last two events.

The DPD pin polarity is determined by the value of ECR14:

●

when ECR14 is cleared (‘0’) the DPD pin is active Low. The DPD pin is active Low by

default.

●

when ECR14 is set (‘1’), the DPD pin is active High.

While in DPD mode:

●

the values of Configuration Register, Enhanced Configuration Register, Block Lock bits

and Bank states are preserved.

●

the Status Register is reset to 80h.

If the Status Register contains errors before entering the DPD mode, the error bits will be

lost after exiting DPD mode.

The device should not be put in Deep Power-Down mode while a program, erase or

suspend operation is in progress. If the device is put in Deep Power-Down mode during a

program, erase or suspend operation, the operation will abort, and the memory contents will

no longer be valid.

The Deep Power-Down mode is exited tDPHEL after de-asserting the DPD pin. On exiting the

Deep Power-Down mode, the memory reverts to the Standby mode.

If the RP pin is asserted while in DPD mode, the device exits DPD mode after tPHEL and

ECR15 is reset to 0.

M58PR256J Datasheet(PDF) 18 Page - STMicroelectronics

M58PR256J Datasheet(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL