UPD360 datasheet(79/221 Pages) MICROCHIP

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DS00002084C-page 79

UPD360

The Rp current sources are disabled on both CC pins via CC1 RP Value or CC2 RP Value.

The Ra pull-down on the CC pin previously sourcing VCONN is selected via CC1 Pull-Down Value or CC2 Pull-

Down Value. This initiates the VCONN discharge.

Software sets the CC threshold 0 to 150 mv (41d), via the CC Threshold x Registers (CC_THRx), which is the

VCONN discharge threshold.

Software programs 01h into the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN).

Software programs 01h into the CCx Match Enable Registers (CCx_MATCH_EN).

Software enables CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via the CC Interrupt Enable Register

(CC_INT_EN).

Via the CC Control Register (CC_CTL), the CC Comparator Control selects the CC pin that was sourcing

VCONN.

10. Changes in state of the CC pin are recorded in CCx Match Registers (CCx_MATCH) and CCx Change Status

Registers (CCx_CHG_STS) after the programmed debounce period.

11. After VCONN discharges below 150mv, IRQ_N asserts which indicates VCONN has been discharged. IRQ_N

assertion of CC_MATCH_VLD with no threshold matches is also indicative of a complete discharge.

12. After the discharge has been completed, the device is in the Unattached.SRC state.

Note:

Software should implement a timer to indicate a VCONN discharge error. This may be implemented using

the General Purpose Timer. While there is no specific requirement in the Type-C specification for a maxi-

mum discharge time

Note:

After the UFP disconnect is detected, firmware must disconnect the VCONN supply within tVconnOff (35

ms) per release 1.1 of the Type-C specification.

9.8

VBUS Detection

The device implements a comparator for determining when VBUS is within a programmed range, vSafe5V, or vSafe0v.

VBUS is divided down externally via a 1:9 resistor divider to generate VBUS_DET. VBUS_DET is compared with an 8-

bit threshold generated by an integrated DAC. The comparator is also shared by the CFG_SEL0 and CFG_SEL1 pins

which are sampled automatically after a system reset

Figure 9-3 illustrates the VBUS_DET circuit. In a typical use case, VBUS_DET thresholds are programmed to track the

following voltage ranges as defined in Table 9-6.

For a DFP, the VBUS comparator is useful to detect when VBUS is within the desired range per PD negotiations. This

is the case when VBUS is generated by a source external to the device.

Note:

Table 9-6 illustrates the values of VBUS_DET utilizing +/-1% accurate resistors where R1 is 10K Ohms and

R2 is 90 kOhms.

FIGURE 9-3:

VBUS_DET COMPARATOR

Bandgap

Reference

CFG_SEL0

CFG_SEL1

VBUS_MATCH/

CFG_MATCH

DAC

VBUS and

CFG_SEL

Threshold

Generation

10-bits

20 KHz Clock

VBUS_DET

VBUS

15 uA

ZTC

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